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2024-04-03vendorcode/amd/opensil: Add CPP args to all stagesArthur Heymans
It does not hurt to do this and makes it possible to link romstage sources into bootblock. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79576 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-23soc/amd/genoa_poc/domain: refactor read_soc_memmap_resourcesFelix Held
To bring genoa_poc more in line with the other AMD SoCs, move the reporting of the memory map up to cbmem_top from the openSIL-specific add_opensil_memmap function to read_soc_memmap_resources. This is a preparation for making this code common for all newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-22vc/amd/opensil/genoa_poc/mpio: add debug output for unused chipFelix Held
Print that the MPIO chip of one of the MPIO-related PCI device functions is unused and is skipped, if the type is IFTYPE_UNUSED and the corresponding PCI device function isn't enabled. This allows to differentiate between this case and the case where the type isn't IFTYPE_UNUSED. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: fix unused MPIO chip warningFelix Held
When the chip of one of the MPIO-related PCI device functions has the type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace 'engine' with 'chip' in the warning. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-22vc/amd/opensil/genoa_poc/mpio: use device status for port_presentFelix Held
Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE macro parameter when the device is enabled; otherwise report the port as disabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: simplify per_device_config argumentsFelix Held
Since we're already passing a pointer to the corresponding device to per_device_config, we don't need to pass the chip_info as separate parameter. Before moving the PCIe port function device below the MPIO chip, the chip_info struct was from a different device, so that change allows this simplification. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-22vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chipFelix Held
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20vc/amd/opensil/*/mpio: add IFTYPE_UNUSED mpio_type enum elementFelix Held
Add IFTYPE_UNUSED as first element to the mpio_type enum. This allows checking if the type was set in the devicetree, since the default will now be IFTYPE_UNUSED. If the type is set to IFTYPE_UNUSED although the corresponding PCI device function, a warning is printed and the PCI device function is disabled. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-20vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type valuesFelix Held
Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more specific names. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-20vc/amd/opensil/stub/mpio: change mpio_engine_type prefix to IFTYPEFelix Held
Change the prefix of the elements of the mpio_engine_type enum from ENGINE_ to IFTYPE_. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a Reviewed-on: https://review.coreboot.org/c/coreboot/+/81346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-17vc/amd/opensil: don't use source path when using stubMarshall Dawson
Add a 'depends on' statement so that path/to/opensil/source is only active when the stub is not built. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic050ff0fa3f428e6adff3357f476fcd8a88cdf7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81189 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-11vc/amd/opensil/stub: add stub MPIO driverFelix Held
Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use GiB defineFelix Held
Use the GiB define to make the 4 GiB boundary used in some places in the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-23vc/amd/opensil/genoa_poc/mpio/chip: fix typo in pcie_aspm enum nameFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I60ac259d2aa0bd500063a5c841ba33e576e022f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80702 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-02vc/amd/opensil: add openSIL stub implementationFelix Held
Add a stub implementation of the openSIL interface between coreboot and vendorcode. This can be used to add most of the coreboot-side support for a SoC using openSIL without the actual opnSIL code already being publicly available. Once the corresponding openSIL code is available, the SoC can then switch over to using the actual openSIL implementation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9284b0cbacba6eae7e2e7e69bc687f015076c2b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80292 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-02-02vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.hFelix Held
Provide 3 separate functions for each openSIL time point instead of one, so that we don't need the xSIM-api header file to be included in opensil.h to decouple the coreboot code more form the openSIL code. This will allow to create an openSIL stub implementation to already get most of the coreboot-side SoC code in place before the openSIL source code is done and released. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-02-01soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resourcesFelix Held
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01vc/amd/opensil/genoa_poc/memmap: pass resource index as pointerFelix Held
To make add_opensil_memmap match the other function that are directly or indirectly called by amd_pci_domain_read_resources, pass the resource index as a pointer instead of passing it by value and then returning the new resource index. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-01vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource indexFelix Held
Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct and the functions to report the resources. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80265 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-25vc/amd/opensil/genoa_poc/mpio: don't add duplicate MPIO descriptorsFelix Held
When the device right below the MPIO chip driver has downstream devices without another chip in between, those downstream devices will also have their chip_ops entry set to vendorcode_amd_opensil_genoa_poc_mpio_ops. To avoid adding the same MPIO descriptor again for those additional downstream devices, make sure that the chip_info pointer of the device isn't the same as the one of the parent device, since that's only the case for those additional downstream devices. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-25soc/amd/genoa_poc: rely less on boot state hooksFelix Held
Call setup_opensil, opensil_entry, and fch_init in the right order from the init method of the SoC's chip operations. This brings this SoC both more in line with the other SoCs and avoids using boot state hooks for this which also makes the sequence in which those functions are called easier to understand. Previously the boot states were used so that setup_opensil was run before configure_mpio which was run before opensil_entry(SIL_TP1), but since configure_mpio is called from setup_opensil, this is no longer necessary. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same. The FCH init code now runs before the resource allocation like on the AMD SoCs that rely on FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensilFelix Held
Instead of calling configure_mpio from the init function of the MPIO chip struct for the first device that has this struct as chip_ops, call if from setup_opensil. This will allow to do the calls into openSIL from the SoC's chip_ops init function instead of having to rely on boot state hooks. configure_mpio needs to be called after the xSimAssignMemoryTp1 call which sets up the openSIL data structures, but before the opensil_entry(SIL_TP1) call for which the MPIO data structures need to be filled for it to be able to initialize the hardware accordingly. Since the vendorcode_amd_opensil_genoa_poc_mpio_ops struct now no longer assigns configure_mpio to the init function pointer, we have to check if the device's chip_ops pointer points to vendorcode_amd_opensil_genoa_poc_mpio_ops instead of checking if the chip_ops' init function is configure_mpio to match for the devices below the MPIO chips in the devicetree. TEST=Onyx still boots to the payload and the MPIO configuration reported from the openSIL code is still the same Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-25vc/amd/opensil/genoa_poc/opensil_console: fix host debug print functionFelix Held
Since we pass va_list list to the print function, we need to use vprintk instead of printk. Earlier versions of this code used vsnprintf and a local buffer, but when that code was reworked to not need the temporary buffer, it was replaced by printk instead of the correct vprintk. TEST=Now the console output from openSIL looks as expected: Example line from openSIL's console output when it prints the MPIO configuration from a log some commits before this patch: Host PCI Address - -1352681400:-1353251983:7 Same line with this patch applied looks how it's supposed to: Host PCI Address - 0:0:0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ia931cc80dea5b7eabb75cfb19f8baa9a09cd2dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/80203 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpioFelix Held
As a preparation for the following patch, rename mpio_config to configure_mpio to make it both a bit more descriptive and to match the naming scheme used for the functions that get called by setup_opensil. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-01-24vendorcode: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I80559b7c86a8fd2583cb0335279f676e0aa0209e Reviewed-on: https://review.coreboot.org/c/coreboot/+/80067 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2023-12-16vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOAFelix Held
The openSIL code for the Genoa SoC is only a proof of concept, so change the name of the Kconfig option to include this code in the build from SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this is code that isn't intended or ready to be productized. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16soc/amd/genoa: rename to genoa_pocFelix Held
Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15vc/amd: use 'openSIL' spelling in comments & help textFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I176182180f508a180726fca60064b16fad80e9d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-14vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_portsFelix Held
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O ports in FADT that openSIL configured. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12vendorcode/amd/genoa: Parse APOB for DRAM layoutArthur Heymans
Use the xPRF call to report holes in memory to report those regions as reserved. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa: Add opensil MPIO chip filesArthur Heymans
Add the openSIL MPIO chip driver that allows specifying the MPIO lane configuration in the mainboard's devicetree instead of having this configuration in a separate port descriptor C file. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12vendorcode/amd/opensil: Add SATA configurationArthur Heymans
For now, we'll use a hard-coded SATA controller configuration that should work in most cases instead of making everything configurable via devicetree settings. In the process of scrubbing opensil for public release SATA became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12vendorcode/amd/opensil: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08vendorcode/amd/opensil: Set up resource manager input blockArthur Heymans
Tell the resource manager in openSIL to distribute the available IO and MMIO ranges across the different PCI root bridges. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-06vendorcode/amd/opensil: Add initial setup and API callsArthur Heymans
- First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-30vendorcode/amd/opensil: Implement cbmem_top_chipsetArthur Heymans
Use an xPRF call to get the top of lower DRAM. Organize Makefile to keep romstage/ramstage components separate. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-30vendorcode/amd/opensil/genoa: Implement console callbackArthur Heymans
OpenSIL has an API to call back into the host firmware to print to the console. These could be moved to a common directory when there are more openSIL implementations to see if it is actually common. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-11-28vendorcode/amd: Hook up opensilArthur Heymans
OpenSIL has a native buildsystem using meson and configuration mechanism using kconfiglib. To be able to use the coreboot toolchain with opensil, meson crossfiles are used, which get generated by coreboot makefiles. Configuration of opensil is done in a similar fashion with a template defconfig after which kconfiglib is called to generate headers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide2d181914116119dfd37b1511d89ea965729141 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-11-13Update genoa_poc/opensil submodule to upstream mainMartin Roth
Updating from commit id d81517e: 2023-09-28 14:13:56 -0600 - (Improper bit field offset calculation) to commit id 0411c75: 2023-11-10 23:59:34 +0000 - (Minor changes to fix issues compiling with clang) This brings in 1 new commits: 0411c75 Minor changes to fix issues compiling with clang Change-Id: Ib3adfd7bccd45dfd76ede462677dcfb294baa15d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-07vc/amd/opensil/genoa_poc/openSIL: Add openSIL code as submoduleMartin Roth
This is a RW mirror of AMD's openSIL for Genoa with additions from Arthur Heymans. - origin/openSIL/main from https://github.com/openSIL/openSIL.git - origin/ArthurHeymans/64b_public from https://github.com/ArthurHeymans/openSIL.git The current main branch starts with Arthur's branch and adds 5 commits from the AMD's openSIL repo. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8917edf3a6a8493ffa9230902cafcc6234d3d571 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 00:12:32 +0000