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The openSIL code for the Genoa SoC is only a proof of concept, so change
the name of the Kconfig option to include this code in the build from
SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this
is code that isn't intended or ready to be productized.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.
Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I176182180f508a180726fca60064b16fad80e9d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O
ports in FADT that openSIL configured.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the xPRF call to report holes in memory to report those regions as
reserved.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the openSIL MPIO chip driver that allows specifying the MPIO lane
configuration in the mainboard's devicetree instead of having this
configuration in a separate port descriptor C file.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For now, we'll use a hard-coded SATA controller configuration that
should work in most cases instead of making everything configurable via
devicetree settings.
In the process of scrubbing opensil for public release SATA became non
functional.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drive board specific USB configuration from the coreboot devicetree into
the opensil input block.
In the process of scrubbing opensil for public release USB became non
functional.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tell the resource manager in openSIL to distribute the available IO and
MMIO ranges across the different PCI root bridges.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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- First a console is set up for opensil.
- After that a region in CBMEM is reserved and passed to opensil which
will use it as a buffer for input/output information.
- Finally opensil is called and the return value handled.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use an xPRF call to get the top of lower DRAM.
Organize Makefile to keep romstage/ramstage components separate.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I269663414f4d8e39eb218cd6348bfce7989a79f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76513
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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OpenSIL has an API to call back into the host firmware to print to the
console.
These could be moved to a common directory when there are more openSIL
implementations to see if it is actually common.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I208eea37ffde64a2311cb9f51e2bcd1ac3dbad4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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OpenSIL has a native buildsystem using meson and configuration mechanism
using kconfiglib.
To be able to use the coreboot toolchain with opensil, meson crossfiles
are used, which get generated by coreboot makefiles.
Configuration of opensil is done in a similar fashion with a template
defconfig after which kconfiglib is called to generate headers.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide2d181914116119dfd37b1511d89ea965729141
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76511
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Updating from commit id d81517e:
2023-09-28 14:13:56 -0600 - (Improper bit field offset calculation)
to commit id 0411c75:
2023-11-10 23:59:34 +0000 - (Minor changes to fix issues compiling with clang)
This brings in 1 new commits:
0411c75 Minor changes to fix issues compiling with clang
Change-Id: Ib3adfd7bccd45dfd76ede462677dcfb294baa15d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This is a RW mirror of AMD's openSIL for Genoa with additions from
Arthur Heymans.
- origin/openSIL/main from
https://github.com/openSIL/openSIL.git
- origin/ArthurHeymans/64b_public from
https://github.com/ArthurHeymans/openSIL.git
The current main branch starts with Arthur's branch and adds 5 commits
from the AMD's openSIL repo.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8917edf3a6a8493ffa9230902cafcc6234d3d571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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