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2021-02-09vc/amd/fsp/cezanne: add FspGuids.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/amd/picasso: add UPD for RV2 USB3 phy setting adjustChris Wang
add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04vendorcode/amd/fsp/cezanne: add UPD structs from FSP buildFelix Held
There will be incompatible changes during the further development of the coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct size to match the one in the FSP header. See CB:50241 for details. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242 Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/amd/picasso: clean up and re-sort UPD tableChris Wang
Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-25soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang
Add UPDs for eDP power sequence adjust. BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-24soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-21soc/amd/picasso: Add UPDs for support eDP phy tunning adjustChris Wang
Add UPDs for eDP phy tunning adjust BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df Reviewed-on: https://review.coreboot.org/c/coreboot/+/48731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-06soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao
Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-30vc/amd/fsp: Update bl_errorcodes_public.hMartin Roth
Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-23vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.hJason Glenesk
Remove all typedefs and cleanup references to all structs and enums. BUG=b:159061802 TEST=Boot morphius to shell. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-07vc/amd/fsp: Update the svc call header for the Mod Exp SVCMartin Roth
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01vc/amd/fsp/picasso: Add bit definitions for PSP info in transfer blockMartin Roth
BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45804 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25vc/amd/fsp/picasso: Update to UPD 1.0.1.3Raul E Rangel
This adds eMMC preset settings. It also fixes some formatting and a comment. BUG=b:159823235 TEST=Build test Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11vc/amd/fsp/picasso: Fix FSP-S UPD header file formattingFelix Held
Use one tab instead of 8 spaces at the beginning of the lines added in commit 39a8040ddc551306d823d52a459fdb5dd717b2fe. Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10vc/amd/fsp/picasso: Sync FSP-S UPD header fileMarshall Dawson
Sync the UPD definitions with the latest auto-generated files. Definitions and usage will be updated in a subsequent FSP Integration Guide. Cq-Depend: chrome-internal:3247431 BUG=b:167421913, b:166519072, b:159664044 TEST=Boot morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-28vc/amd/fsp/picasso: Add FSP-M UPD enable_sata to 0xC7 to match FSPNikolai Vyssotski
BUG=b:162302027 BRANCH=zork Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668 Cq-Depend: chrome-internal:3201648 Cq-Depend: chrome-internal:3202602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23vc/amd/fsp/picasso: add FSP-M UPD to disable the HD Audio controllerFelix Held
BUG=b:158535201,b:162302028 BRANCH=zork Change-Id: If4886591b7d73293773e4d36ec653ef42e8b2f54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44679 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23Revert "vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controller"Felix Held
This reverts commit 65605276a4cd08fd2e38f87cd80e3362265f9091. This patch shouldn't have been merged yet, since the issues on the FSP side aren't sorted out yet, so the FSP-side changes haven't landed yet. This byte will be used for an audio-related setting instead to have the audio settings grouped together. BRANCH=zork Change-Id: If79900f3a92fd949d7653001e1ca2faac7061e3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44678 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19vc/amd/fsp/picasso: update pci descriptor commentsMatt Papageorge
Update fsp_dxio_descriptor comments to be more comprehensive of the currently available data fields. Most of these are not currently utilized with Zork but may be in future projects. BUG=b:161218965 TEST=Build test Trembyle Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controllerFelix Held
BUG=b:162302027 Change-Id: Iff9a09cb59fdc16be8b4ea41303704166a97172e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13vc/amd/picasso/bl_uapp: Update header fileMarshall Dawson
Update to match the 0.8.6.7B release of PSP blobs. BUG=b:163857965,b:137123167 TEST=Boot Trembyle, run SST Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-05vendorcode/amd/fsp/picasso Fix type 17 smbios misalignmentJason Glenesk
Add __packed to TYPE17_DMI_INFO structure to remove padding. Remove reserved fields that are no longer required. Corresponding change will also be made within fsp to pack the structure. BUG=b:154046847 TEST=Boot a trembyle with and without the reserved fields and confirm type 17 table is unchanged. Cq-Depend: chrome-internal:3194239 Change-Id: I9ba7e2a4fb82c7b0b77ee7c6c075e6211d4f6adf Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-08-02vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignmentsFelix Held
Also document the maximum nuber of lanes for the different platforms. Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31vc/amd/fsp/picasso: document DXIO lane number mappingFelix Held
Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme. Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30vc/amd/picasso/bl_uapp: Update header fileMarshall Dawson
Update to match the 0.8.5.7B release of PSP blobs. BUG=b:162057232 TEST=Boot Trembyle with, and without, new blobs. Inspect vboot using a serial-enabled bootloader Change-Id: I03f11cfc1dc8f511661def1c81421f8558dcd1f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44041 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24vc/amd/fsp/picasso: update UPD headerFelix Held
A new version of UPD headers generated from the FSP tree. This adds UPDs for downcoring and increases the number of DXIO descriptor slots. BUG=b:161152720 TEST=SATA on Mandolin works now. Cq-Depend: chrome-internal:3175393 Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-22vc/amd/fsp/picasso: mark remaining UPD header structs as __packedFelix Held
Change-Id: I5a97de69bfda201e039587c67037bfb93ca16c15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43658 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15amd/picasso: rework DXIO and DDI UPD handlingFelix Held
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct into arrays allows to properly iterate over the fields. BUG=b:158695393 TEST=Mandolin still boots. Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15vc/amd/fsp/picasso: replace #pragma pack(1) with __packed attributeFelix Held
Forgetting to add the #pragma pack() at the end of the header file can lead to hard to debug breakage, so get rid of the #pragma pack usage and add a __packed to the structs that need to be packed which has less possibly unwanted side effects. Since commit d44221f9c8f3686e040ff9481829315068b321a3 coreboot always includes commonlib/compiler.h which provides __packed. TEST=Timeless build results in identical binary. Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12vc/amd/fsp/picasso: add DMI data structure definitionsAaron Durbin
Provide the data structures for parsing SPD information supplied by FSP. BUG=b:160947978 Change-Id: If847646625448547599018a823712d5c14e4bd76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43350 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09vc/amd/fsp/picasso: add comment on logical lane numbers in descriptorFelix Held
The expected lane numbers in the fsp_pcie_descriptor struct are the logical and not the physical ones. Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43311 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22vc/amd/fsp/picasso: Sync UPD and GUID filesMarshall Dawson
Update to the latest auto-generated UPD files. Add the GUID for the BERT HOB now being reported. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ia01f626bc85696483173b567bb4f06d308832a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19vc/amd/fsp/picasso: Use fixed width fields for platform descriptorsMatt Papageorge
PCIe platform descriptors passed to Picasso FSP should use fixed width fields. BUG=b:153681134 TEST=Boot system and suspend/resume. All PCIe devices train succesfully. Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Change-Id: If2a34be895db2c19c8830f5888cb99e43ad21b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42519 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15vc/amd/fsp/picasso: Add AMD code to support psp_verstageMartin Roth
Add the AMD supplied code (modified to work with GCC) to the vendorcode directory. Verstage will be running on the PSP as a userspace application under the bootloader, which is what bl_uapp signifies. AMD is still working on documentation for the entire PSP userspace application interface. BUG=b:158124527 TEST=Build & boot psp_verstage on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie740c89afe2277eff279fc5c94f88ffd43a78a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02soc/amd/picasso: Install AGESA ACPI tablesMatt Papageorge
AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-24vc/amd/fsp/picasso: add Picasso misc data HOB GUID and structFelix Held
BUG=b:153779573 Change-Id: I417ce34f2c302d61cfe94ff478f9022cae16f046 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41629 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21vc/amd/fsp/picasso: Rename the fsp_ddi and fsp_pcie descriptorsRaul E Rangel
This change was missed when I ported over fsp_params.c. BUG=b:157140753 TEST=Boot trembyle to OS Fixes: 89e51e61781 ("soc/amd/picasso: Allow mainboard to provide pci ddi descriptors") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icdb6aebe5a3be7174170bdf37a1f379f02dcc5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38Marshall Dawson
Include a more recent set of files from a current FSP build. These are automatically generated. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6428f618afc2a1cf1c35e93e00f905f90b2cd86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38696 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16vc/amd/fsp/picasso: Add file for GUIDsMarshall Dawson
Begin a file for GUIDs used by the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38697 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-27vc/amd/fsp/picasso: Add PCIe and DDI helpersMarshall Dawson
Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-10-20vc/amd/fsp: Add UPD header files for picassoMarshall Dawson
Add files for Picasso's FSP UPD definitions. These are automatically generated from the FSP build. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34575 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 07:03:05 +0000