diff options
| author | Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> | 2020-06-16 15:45:40 -0500 |
|---|---|---|
| committer | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-06-19 16:38:27 +0000 |
| commit | 02f7471b19c57c01d02343be9c09b4a9ea8c6fb9 (patch) | |
| tree | 3531b22fe4f091ea5ffcb6f5c7dd96f8b575b489 /src/vendorcode/amd/fsp | |
| parent | b8fba86b143b471a2126411177b0236f08358b8e (diff) | |
vc/amd/fsp/picasso: Use fixed width fields for platform descriptors
PCIe platform descriptors passed to Picasso FSP should use fixed width fields.
BUG=b:153681134
TEST=Boot system and suspend/resume. All PCIe devices train succesfully.
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: If2a34be895db2c19c8830f5888cb99e43ad21b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42519
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp')
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/platform_descriptors.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 8a701948dd..cae5d45bd8 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -115,27 +115,27 @@ typedef struct __packed { uint8_t start_lane; // Start lane of the pci device uint8_t end_lane; // End lane of the pci device uint8_t gpio_group_id; // FCH reset number. 0 is global reset - unsigned int port_present :1; // Should be TRUE if train link - unsigned int reserved_3 :7; - unsigned int device_number :5; // Desired root port device number - unsigned int function_number :3; // Desired root port function number - unsigned int link_speed_capability :2; - unsigned int auto_spd_change :2; - unsigned int eq_preset :4; - unsigned int link_aspm :2; - unsigned int link_aspm_L1_1 :1; - unsigned int link_aspm_L1_2 :1; - unsigned int clk_req :4; + uint32_t port_present :1; // Should be TRUE if train link + uint32_t reserved_3 :7; + uint32_t device_number :5; // Desired root port device number + uint32_t function_number :3; // Desired root port function number + uint32_t link_speed_capability :2; + uint32_t auto_spd_change :2; + uint32_t eq_preset :4; + uint32_t link_aspm :2; + uint32_t link_aspm_L1_1 :1; + uint32_t link_aspm_L1_2 :1; + uint32_t clk_req :4; uint8_t link_hotplug; uint8_t slot_power_limit; - unsigned int slot_power_limit_scale :2; - unsigned int reserved_4 :6; - unsigned int link_compliance_mode :1; - unsigned int link_safe_mode :1; - unsigned int sb_link :1; - unsigned int clk_pm_support :1; - unsigned int channel_type :3; - unsigned int turn_off_unused_lanes :1; + uint32_t slot_power_limit_scale :2; + uint32_t reserved_4 :6; + uint32_t link_compliance_mode :1; + uint32_t link_safe_mode :1; + uint32_t sb_link :1; + uint32_t clk_pm_support :1; + uint32_t channel_type :3; + uint32_t turn_off_unused_lanes :1; uint8_t reserved[4]; } fsp_pcie_descriptor; |