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2017-04-08AGESA f14: Fix memory clock register decodingKyösti Mälkki
Bottom five LSBs are used to store the running frequency of memory clock. Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06AGESA f14: Fix MemContext buffer parser for AmdInitPost()Kyösti Mälkki
Memory training data that is saved as part of S3 feature in SPI flash can be used to bypass training on normal boot path as well. When RegisterSize is 3 in the register playback tables, no register is saved or restored. Instead a function is called to do certain things in the save and resume sequence. Previously, this was overlooked, and the pointer containing the current OrMask was still incremented by 3 bytes. Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09AGESA: Use printk for IDS outputKyösti Mälkki
In all simplicity, with board/OptionsIds.h file having: IDSOPT_IDS_ENABLED TRUE IDSOPT_TRACING_ENABLED TRUE And src/Kconfig modified to: config WARNINGS_ARE_ERRORS default n With these settings AGESA outputs complete debugging log where-ever you have your coreboot console configured. Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15320 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2017-03-09AGESA: Make eventlog more tolerant to failuresKyösti Mälkki
We have been forced to build AGESA with ASSERT() as non-fatal for some board, as hitting those errors is not uncommon. For the cases touched here, abort eventlog operations early to avoid further errors and dereference of null pointers. Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18543 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09AGESA: Apply a threshold on event loggingKyösti Mälkki
Implement threshold as described in AMD.h, and do not add entries below STATUS_LOG_LEVEL in the eventlog. Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18542 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-07Stage rules.h: Add ENV_LIBAGESAKyösti Mälkki
Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14AGESA: Remove nonexistent include pathKyösti Mälkki
Change-Id: I3395e274e0ba43de7e7306daedeb26c75de65ee1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18327 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-13vendorcode/amd/agesa: Remove flawed warningŁukasz Dobrowolski
The compilation would fail if CFG_MEMORY_LRDIMM_CAPABLE == FALSE and BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE. Change-Id: I1be37e368bc4ed07e59d0f0bb967bed11143a65b Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17354 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-11-22src/vendorcode/amd/agesa: Fix castingŁukasz Dobrowolski
When IDSOPT_TRACING_ENABLED is TRUE build fails with "cast from pointer to integer of different size" Use "UINTN" as is done in Family 16h. Change-Id: I362e67fc83aa609155f959535f33be9c150c7636 Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17406 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-02vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLEŁukasz Dobrowolski
String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17118 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-22amd/agesa/f16kb: Allow SATA Gen3Fabian Kunkel
YangtzeSataResetService implements the SataSetMaxGen2 double. The value should be only set, if the condition is met. For testing, add FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE; to your BiosCallOuts.c, which enables GEN3 for the SATA ports. Patch is tested with bap/e20xx board, Lubuntu 16.04 Kernel 4.4. $ dmesg | grep ahci #before patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode $ dmesg | grep ahci #after patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode Change-Id: I17a493b876a4be3236736b2116b331e465b159af Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15728 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-01AGESA boards: Fix split to romstage and ramstageKyösti Mälkki
Boards broken with commit: 062ef1c AGESA boards: Split dispatcher to romstage and ramstage Boot failure with asus/f2a85-m witnessed around MemMS3Save() call, message "Save memory S3 data in heap" in verbose agesa logs was replaced by a system reset. Default stubs for MemS3ResumeConstructNBBlock() returned TRUE without initializing the block contents. This would not work for case with multiple NB support built into same firmware. MemMCreateS3NbBlock() then returned with S3NBPtr!=NULL with uninitialized data and MemMContextSave() referenced those as invalid pointers. There is no reason to prevent booting in the case S3 resume data is not passed to ramstage, so remove the ASSERT(). It only affects builds with IDSOPT_IDS_ENABLED=TRUE anyways. Change-Id: I8fd1e308ceab2b6f4b4c90f0f712934c2918d92d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA f12 f15: Add OEM customisationKyösti Mälkki
Follow-up on commits a5d72a3 and 53052fe for f12 and f15. OEM Hooks are not BiosCallOuts. Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14888 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Fix invalid BLDCFG_ and CFG_ useKyösti Mälkki
The definitions of CFG_ would evaluate to incorrect values when Options.h is included outside buildOpts.c, where all BLDCFG_ values are defined. Already done for f16kb. Change-Id: I5d725b9306027c7c46c6450ab17b692fa948cf5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14886 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Drop unused assembly filesKyösti Mälkki
Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Remove unused platform configuration filesKyösti Mälkki
Change-Id: Ie6effa802f6971c59b5c4e07ca7d98736e27859f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14885 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA f10: Pick sample platform configurationKyösti Mälkki
Tree does not have any AGESA f10 boards. Keep the Danube platform as a sample configuration file for unlikely future use. Change-Id: I025aff48fcd0884b45e2a0a993d82f317ede48be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18AGESA vendorcode: Move compiler class definitionKyösti Mälkki
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-13AMD fam14: Blacklist Intel Centrino n6235 from PCIe ASPMKyösti Mälkki
PCI device ID of this mini-PCI-e WLAN card is 8086:088e. With this card inserted on pcengines/apu1 mini-PCI-e slot J17, system halts late in ramstage, in agesawrapper AMD_INIT_MID. Offending operation is enabling PCIe ASPM L0s and L1 for the card. That is, writing PCIe capability block Link Control [1:0] = 11b in the card's configuration space. AGESA already has a blacklist for the purpose of masking such unstable ASPM implementations. Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/8496 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA vendorcode: Drop alternate image dispatcherKyösti Mälkki
Not used as we link AGESA into same romstage and ramstage ELF. Change-Id: Ia427b9c0cc88b870de75df14bba4ca337a28adff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA f12: Build as libagesa.aKyösti Mälkki
Change-Id: If48fffee1441b6bb012a8d99abb794f7a35efcf6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14412 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA f16kb: Build as libagesa.aKyösti Mälkki
Change-Id: I9faeda508694f950f1b025765e2ac63bc91747fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10AGESA boards: Relocate platform memory configKyösti Mälkki
File buildOpts.c is a can of worms, pull platform memory configuration in to OemCustomize.c. This array should be assigned at runtime instead of linking a modified defaults table. Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21AGESA vendorcode: Fix type mismatchKyösti Mälkki
Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14416 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20AGESA vendorcode: Suppress maybe-uninitialized warningsKyösti Mälkki
Compiling libagesa with -O2 would throws error on these. Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14413 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20AGESA vendorcode: Fix logic errorKyösti Mälkki
We have not really hit this error, due the test on AGESA_UNSUPPORTED above. Change-Id: I6e7d136a1bb46138cc347225bc4c82cfeaff385d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16vendorcode/amd/agesa: Fix tautological compareEdward O'Callaghan
An unsigned enum expression is always strictly positive; Comparison with '>= 0' is a tautology, hence remove it. Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/8207 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-31vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in commentPaul Menzel
The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/5543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-02-03vendorcode/amd/agesa/f1{4,2,0} Sync Include directoryEdward O'Callaghan
Sync and merge useless differences. Change-Id: I4eea66c35af66d473dd56db9ccf105c878266f22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/7513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-03vendorcode/amd/agesa/f15?tn: Strip false/redudant AMD ver tagEdward O'Callaghan
Strip out the AMD internal version tag, e.g. * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ which are false/inconsistent and serve no real meaning or purpose now. Change-Id: I4cca0899eba66a1c361ba784c5ac0222b0ee1aa6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/7516 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltageMartin Roth
I think this has a fairly low likelyhood of happening, but if AGESA can't determine the voltage of the memory, it assignes a value of 255 to the variable that it later uses to read from an 3-value array. There is an assert, but that doesn't halt AGESA, so it would use some random value. If the voltage can't be determined, fall back to 1.5v as the default value. Fixes coverity warning 1294803 - Out-of-bounds read Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12855 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07src/vendorcode/amd: correct spelling of MTRRPaul Menzel
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07f14: Increase AP stack to 8k on 64bitStefan Reinauer
This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://review.coreboot.org/11025 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop unused code from gcc-intrin.hStefan Reinauer
Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11108 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd: Fix cbtypes.h to match UINTN conventionStefan Reinauer
There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30vendorcode/amd: 64bit fixesStefan Reinauer
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-09f10/f12: Remove whitespace from gcccar.incStefan Reinauer
:'<,'>s,\ *$,, Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-30vendorcode: Port AMD Agesa for Fam14 to 64bitStefan Reinauer
Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10581 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-23vendorcode: Use cross archiver for libagesa.a on AMD f14Stefan Reinauer
Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10593 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-10vendorcode/amd/agesa/f16kb: Enable support for AM1 socketSergej Ivanov
Adds option FORCE_AM1_SOCKET_SUPPORT to disable package type mismatch check between cpu and northbridge. Default agesa for kabini doesn't know about AM1 socket so it returns FALSE, that stops memory config code. With this hack current agesa version supports the AM1 socket. Change-Id: I99e9cec5cd558087092cf195094df20489f6d3b5 Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: http://review.coreboot.org/9291 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-03-07AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2Kyösti Mälkki
Make the build tolerate re-definitions. Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-01-31vendorcode/amd/agesa/f14: update microcodeNicolas Reinecke
05000028 -> 05000029 tested on asrock E350M1 05000101 -> 05000119 Change-Id: Iccb096eb55a4a789c1e810f68c8c8eacfd5f8a0b Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8296 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-14vendorcode/amd/agesa: Remove UCODE_VS_FLAG() macro unused variableEdward O'Callaghan
Remove useless AGESA microcode macro that leads to unused variable warnings. Change-Id: Ia21bfc758f81e349bdd0bfd185df75e8b1898336 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8200 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-12-22amd/agesa/f15/Proc/Common/S3SaveState.c: Sync with f15tnEdward O'Callaghan
Change-Id: If46079c1affc7d74767c4215467fd6754b24f20c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7576 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-18AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-12-16amd/agesa/f*/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
As is the case in commit: 3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Also fix an infinite loop. Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7676 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-10vendorcode/amd/agesa/f16kb/*/PcieComplexDataKB.c: Implicit truncationEdward O'Callaghan
Clang complains: "implicit truncation from 'int' to bitfield changes value from -1 to 15" -1 is define in 'c11std 6.3.1.3p2' as: [Signed and unsigned integers] Otherwise, if the new type is unsigned, the value is converted by repeatedly adding or subtracting one more than the maximum value that can be represented in the new type until the value is in the range of the new type.60) FOOTNOTE.60 The rules describe arithmetic on the mathem... This is "0xFF" on Mullins and "0xF" in this case. Clang seems to complain about this two's complement in a bitfield as being truncated. As the bitfield is 4 bits wide, (a maximum of 15 decimal), we set the field as '0x0F'. Ideally this field /should/ be set to 'UINT8_MAX' however we still have silly truncation warnings. Change-Id: Ib7476d453ffd932bb911e638117cf9f56f71f269 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7719 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-08vendorcode/amd/agesa/fam10: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7699 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08vendorcode/amd/agesa/fam15: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warnEdward O'Callaghan
Add decorations to specify that empty loop is intended so. Change-Id: Ia3e40d341eca5e26da3832edc733cf1ccc96c136 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7688 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07vendorcode/amd/agesa/f15tn/*/F15TnMsrTables.c: Topology Extensions SupportEdward O'Callaghan
Topology Extensions Support (bit 54 of 0xC0011005) applies to PACKAGE_TYPE_FS1r2 also. Rids us of: "Re-enabling disabled Topology Extensions Support" showing up in dmesg. Change-Id: Id123fa9632936c150cf1aebc4d34b404a4398ead Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7671 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-06vendorcode/amd/agesa: Remove unused helper.c fileAlexandru Gagniuc
The contents of these files were guarded by a check for the _MSC_VER macro, which we don't use. Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7670 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-06vendorcode/amd/agesa: Make Porting.h common between familiesEdward O'Callaghan
Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7594 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-06vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilationEdward O'Callaghan
Missing IOMMU support is missing from the libagesa Makefile, it also lacks a header with type-signature and a few bad typecast issues. Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Co-Author: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/7642 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06vendorcode/amd/agesa/fam15tn: Clean #includes in public headersAlexandru Gagniuc
Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5424 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-05vendorcode/amd/agesa/f15tn: Trim out ASCII art in GnbIommuScratch.cEdward O'Callaghan
TL;DR ASCII art that sucks, remove it. Change-Id: I424736b040fe019bba6155de76903225a266760d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7641 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-04vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementationEdward O'Callaghan
We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-28Use AMD_F15_TN_A0 define in FTnLogicalIdTables.cEdward O'Callaghan
Change-Id: I6b20ded866fa0418bd24ce9eef3775557c2feec7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7562 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27vendorcode/amd/agesa: Use F15TN AGESA for F15RLEdward O'Callaghan
For the moment we make use of Trinity f15tn AGESA for Richland f15rl support until we have properly worked out the discrepancies. Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup. We later wish to merge f15tn and f15rl support into the AGESA in any case. Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7559 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2014-11-20vendorcode/amd/agesa/f15?tn: Reduce useless differencesSara Lelliott
Reduce inconsequential differences between fam15 and fam15tn to better prepare for possible merger. Change-Id: I016aa1a4cc45553d51190988d48c8a54cfd85f5a Signed-off-by: Sara Lelliott <sara@jupitercrash.org> Reviewed-on: http://review.coreboot.org/7503 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-20vendorcode/amd/agesa/f*/Porting.h: Sync files across fam'sEdward O'Callaghan
Sync up these 'Porting.h' headers to include fixes from each family on botched-up typedef's for primitive data types. Fix corresponding breakage introduced by typecasts in mainboards. Change-Id: I003b155cc6c860f6b0cd75667083634a04814473 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7512 Tested-by: build bot (Jenkins)
2014-11-19vendorcode/amd/agesa/f15tn: Fix assembly bugsDamien Zammit
Found missing '$' symbol on variable. Change-Id: I748c315adc44598e16283f8e629be0ecfe9cb6a9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7514 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19vendorcode/amd/agesa/f15tn: Remove extraneous bracketDamien Zammit
Found an extra bracket that appears it should not be there. Change-Id: I66b7967833afd25f12bd4eaaf6419a6ed3ad544b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7515 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-13AMD Trinity: Update the Trinity SMU FirmwareZheng Bao
Change-Id: I059047390e80e084f5d7763259d918446d96931e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7294 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-13vendorcode/amd/agesa/f1{0,2,4,5}: Typo in header guardEdward O'Callaghan
Change-Id: I05d568f27f610c395e2638e79a7fd6646a407955 Found-by: Clang preprocessor wizard powers Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7441 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-11AMD Kabini: Update SMU firmware from 0.4 to 0.9Zheng Bao
Version 0.9 contains a fix for a security issue. A more detailed changelog is not available. Change-Id: I1a66c9da900f89ba9b4c13f3457582278d3793e2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7293 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2014-11-10AGESA f14: Add "const" modifiersEdward O'Callaghan
Apply commit 283ba78415 to f14 (literally, plus one adaptation). Change-Id: Ieea47470e5852ec8a46596ce23a2d18444618624 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7361 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-04amd/agesa/f16kb: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7302 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03AGESA f12: Add "const" modifiersPatrick Georgi
Apply commit 283ba78415 to f12 (literally, plus one adaptation). Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7312 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f15: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I52da16b39293c8aeff150db83b8b1aeaa232c205 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7299 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f12: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ife26fb5eca5164e72b5e55eba90757253765b633 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7300 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f10: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ic1bd19087a4500ba0ca9e312ea351e301ab42518 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7301 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-22AGESA fam15tn fam16kb: Fix missing FCH function prototypesKyösti Mälkki
Change-Id: I242664032d368794d828fce73a20f75ded45051d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7151 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-18vendorcode/amd/agesa: Use macros already defined in stdlib.hEdward O'Callaghan
We already have these macros define in 'stdlib.h'. Make good use of them here to avoid redefinition conflicts of the pre-processor depending on header inclusion ordering. This has the nice side-effect of syncing up AGESA families in this particular regard. Change-Id: Icf911629a4a1a82b01062fe16af4c8f812b05717 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6199 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-07-11vendorcode/amd/agesa/f15tn: Fix erratum #712Rudolf Marek
Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller Sequencing The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may be processor specific and may be sensitive to temperature. Potential Effect on System: System hang. Suggested Workaround: BIOS should set D18F2x408_dct[1:0] bit 31 = 1b. See Publication # 48931 Revision: 3.08 Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/6216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10vendorcode/amd/agesa/f14: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Ic63c456e775ad0863ea773abd957d9399e8e2a13 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6191 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f14: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: I716253fe8532a4215e5770cd901ee3b3c4963d3d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6187 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f12: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Iace2ccfe95bd7f7e5dabbbc69ee4249d80d1cb84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6190 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f12: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: Ieca3358a2a459016b7a38dce7f717100b55baba5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6186 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6189 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6185 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-14amd/agesa/f15tn: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5941 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.cEdward O'Callaghan
Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5802 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22vendorcode/amd/agesa/f*: Fix typo in header guardsEdward O'Callaghan
_CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H Spotted by Clang Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5818 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21amd/agesa/*/gcc-intrin.h: Invaild inline asmEdward O'Callaghan
The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible. N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly. The %b and %w constraints are also redundant and only hide errors. The functions writefsword() and writefsdword() should use ir instead of iq. iq is unnecessarily restrictive (it is only required for writing bytes). The cld in stosb is redundant (and the constraints are unnecessarily complicated). Note that The ABI guarantees that the direction flag is cleared. i.e. eax, ecx, edx are caller-saved, returned value in eax, eax+edx, st0, yaddayadda, direction flag cleared. In fact bad things can happen if you set it in some asm and do not clear it until the end of the asm. Line wrap these extraneously long lines found with these particular functions. Many thanks to Christoph Mallon <christoph.mallon@gmx.de> from #llvm for helping me with this. Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5801 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21vendorcode/amd/agesa: unsigned enum is strictly positiveEdward O'Callaghan
The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter 'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant comparison of unsigned enum expression >= 0 is always true. BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5757 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdpEdward O'Callaghan
The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk. However, MinDeltaSclk incorrectly self-assigns. Change-Id: Id01c792057681516bba411adec268769a3549aa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5752 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-05-19amd/agesa: Implicit assigment between enum without castEdward O'Callaghan
Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.hEdward O'Callaghan
Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19vendorcode/amd: kill some intermediate variables in build systemPatrick Georgi
They don't exactly add clarity, but increase the risk they're used at some obscure place. Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5787 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19build: move include paths where they belongPatrick Georgi
They're _not_ part of the compiler binary, so they have no place in $(CC_*) Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19agesa: drop non-existing search pathsPatrick Georgi
With the upcoming CC/CFLAGS/CPPFLAGS split, romcc gets more CPPFLAGS, and it's picky about directories actually existing. Change-Id: Ib9c525296e5be0c8ace935ab8096bc98206cbcc1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5784 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-22 15:00:26 +0000