coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-02	vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile	Mike Banon
2020-12-02	vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles	Mike Banon
2020-08-26	vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table	Mike Banon
2020-07-09	vc/amd/agesa/f15tn: Drop dead code	Angel Pons
2020-03-04	vc/amd/agesa: Delete mfParallelTraining.c	Joe Moore
2020-03-04	vc/amd/agesa/[...]/Proc/Mem: Delete unused function	Joe Moore
2020-01-13	vc/amd/agesa: Fix out of bounds read	Joe Moore
2019-07-19	src: Make implicit fall throughs explicit	Jacob Garber
2018-12-18	Fix typos involving "the the"	Jonathan Neuschäfer
2017-08-31	AGESA f15tn vendorcode: Split to Makefile.inc files	Kyösti Mälkki
2017-08-16	AGESA f15tn: Fix MemContext buffer parser for AmdInitPost()	Kyösti Mälkki
2017-08-04	AGESA f15 f15tn f16kb: Add extra checks for incorrect SPD data	Konstantin Aladyshev
2017-08-02	AGESA: Correct PCI function number for MEM_GET(SET)REG outputs	Konstantin Aladyshev
2016-07-01	AGESA boards: Fix split to romstage and ramstage	Kyösti Mälkki
2016-06-04	AGESA: Drop unused assembly files	Kyösti Mälkki
2016-04-20	AGESA vendorcode: Suppress maybe-uninitialized warnings	Kyösti Mälkki
2016-04-16	vendorcode/amd/agesa: Fix tautological compare	Edward O'Callaghan
2016-02-03	vendorcode/amd/agesa/f15?tn: Strip false/redudant AMD ver tag	Edward O'Callaghan
2016-01-08	vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltage	Martin Roth
2014-12-07	vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warn	Edward O'Callaghan
2014-11-20	vendorcode/amd/agesa/f15?tn: Reduce useless differences	Sara Lelliott
2014-07-18	vendorcode/amd/agesa: Use macros already defined in stdlib.h	Edward O'Callaghan
2013-06-09	fam15 vendorcode: Change license to BSD from AMD software license	Siyuan Wang
2013-01-22	F15tn: Fix all warnings, enable warnings as errors	Martin Roth
2012-07-03	AGESA F15tn: AMD family15 AGESA code for Trinity	zbao