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2017-08-28AGESA f10 vendorcode: Remove refcode sourcesKyösti Mälkki
We never had a board in the tree that implements this. Change-Id: Idce32a20c24e31eb52f8509d4a7cccfc24cf17cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-15vendorcode/amd/agesa: Tidy up gcccar.incKyösti Mälkki
Change register preservations and fix comments about register usage accordingly. Do this to avoid use of %mm0-2 registers inside macros defined in gcccar.inc, as future implementation of C_BOOTBLOCK_ENVIRONMENT will use them as well. Adjust caller side accordingly. Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-07-15vendorcode/amd/agesa: Clarify CAR disableMarc Jones
Clean up commentary on AMD_DISABLE_STACK to be clear that it does a wbinvd to preserve coreboot CBMEM and value of car_migrated. Change-Id: I0f5e9c807f7990fcd5ca85f77b9d92312e775d3e Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20578 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-15vendorcode/amd/agesa: Sync irrelevant differencesKyösti Mälkki
After modifications: f12 and f14 are identical f10 is f14 with invd -> wbinvd modification added to HOOK_F10 f15 is f10 with invd -> wbinvd modification added to HOOK_F15 f15tn is f15 modified to use with TN / KV / KM Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-08src/vendorcode: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I891cb4f799aaafcf4a0dd91b5533d2f8db7f3d61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-26vendorcode/amd: Drop multiple copies of gcc-intrin.hStefan Reinauer
Change-Id: Ifc6a0638c03fa5f3e1007a844e56dfa6f4c71d7e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-26vendorcode/amd: Unify gcc-intrin.hStefan Reinauer
Most of these functions go unused most of the time, but in order to not keep several copies around, let's make sure we are using the same file everywhere first. Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-09AGESA: Make eventlog more tolerant to failuresKyösti Mälkki
We have been forced to build AGESA with ASSERT() as non-fatal for some board, as hitting those errors is not uncommon. For the cases touched here, abort eventlog operations early to avoid further errors and dereference of null pointers. Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18543 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09AGESA: Apply a threshold on event loggingKyösti Mälkki
Implement threshold as described in AMD.h, and do not add entries below STATUS_LOG_LEVEL in the eventlog. Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18542 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-02-14AGESA: Remove nonexistent include pathKyösti Mälkki
Change-Id: I3395e274e0ba43de7e7306daedeb26c75de65ee1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18327 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-22src/vendorcode/amd/agesa: Fix castingŁukasz Dobrowolski
When IDSOPT_TRACING_ENABLED is TRUE build fails with "cast from pointer to integer of different size" Use "UINTN" as is done in Family 16h. Change-Id: I362e67fc83aa609155f959535f33be9c150c7636 Signed-off-by: Łukasz Dobrowolski <lukasz@dobrowolski.io> Reviewed-on: https://review.coreboot.org/17406 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Fix invalid BLDCFG_ and CFG_ useKyösti Mälkki
The definitions of CFG_ would evaluate to incorrect values when Options.h is included outside buildOpts.c, where all BLDCFG_ values are defined. Already done for f16kb. Change-Id: I5d725b9306027c7c46c6450ab17b692fa948cf5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14886 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Drop unused assembly filesKyösti Mälkki
Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA: Remove unused platform configuration filesKyösti Mälkki
Change-Id: Ie6effa802f6971c59b5c4e07ca7d98736e27859f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14885 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04AGESA f10: Pick sample platform configurationKyösti Mälkki
Tree does not have any AGESA f10 boards. Keep the Danube platform as a sample configuration file for unlikely future use. Change-Id: I025aff48fcd0884b45e2a0a993d82f317ede48be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18AGESA vendorcode: Move compiler class definitionKyösti Mälkki
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-12AGESA vendorcode: Drop alternate image dispatcherKyösti Mälkki
Not used as we link AGESA into same romstage and ramstage ELF. Change-Id: Ia427b9c0cc88b870de75df14bba4ca337a28adff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21AGESA vendorcode: Fix type mismatchKyösti Mälkki
Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14416 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20AGESA vendorcode: Suppress maybe-uninitialized warningsKyösti Mälkki
Compiling libagesa with -O2 would throws error on these. Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14413 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20AGESA vendorcode: Fix logic errorKyösti Mälkki
We have not really hit this error, due the test on AGESA_UNSUPPORTED above. Change-Id: I6e7d136a1bb46138cc347225bc4c82cfeaff385d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16vendorcode/amd/agesa: Fix tautological compareEdward O'Callaghan
An unsigned enum expression is always strictly positive; Comparison with '>= 0' is a tautology, hence remove it. Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/8207 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-31vendorcode/amd/agesa/*/AGESA.h: Correct "ne" to "be" in commentPaul Menzel
The typo is not present anymore in Family 16h (Kabini), so fix it for the older families (Family 10h, 12h, 14h, 15h, 15h Trinity) too using the command below. $ git grep -l ' ne ' src/vendorcode/amd/agesa | xargs sed -i 's/ ne / be /g' Change-Id: I9cb419251eeec79925f48a5832fac339d40f01d1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/5543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-02-03vendorcode/amd/agesa/f1{4,2,0} Sync Include directoryEdward O'Callaghan
Sync and merge useless differences. Change-Id: I4eea66c35af66d473dd56db9ccf105c878266f22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/7513 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07src/vendorcode/amd: correct spelling of MTRRPaul Menzel
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30vendorcode/amd: 64bit fixesStefan Reinauer
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-08-09f10/f12: Remove whitespace from gcccar.incStefan Reinauer
:'<,'>s,\ *$,, Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-07AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2Kyösti Mälkki
Make the build tolerate re-definitions. Change-Id: Ia7505837c70b1f749262508b26576e95c7865576 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-16amd/agesa/f*/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
As is the case in commit: 3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Also fix an infinite loop. Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7676 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08vendorcode/amd/agesa/fam10: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7699 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06vendorcode/amd/agesa: Make Porting.h common between familiesEdward O'Callaghan
Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7594 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-04vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementationEdward O'Callaghan
We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-20vendorcode/amd/agesa/f*/Porting.h: Sync files across fam'sEdward O'Callaghan
Sync up these 'Porting.h' headers to include fixes from each family on botched-up typedef's for primitive data types. Fix corresponding breakage introduced by typecasts in mainboards. Change-Id: I003b155cc6c860f6b0cd75667083634a04814473 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7512 Tested-by: build bot (Jenkins)
2014-11-13vendorcode/amd/agesa/f1{0,2,4,5}: Typo in header guardEdward O'Callaghan
Change-Id: I05d568f27f610c395e2638e79a7fd6646a407955 Found-by: Clang preprocessor wizard powers Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7441 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-02amd/agesa/f10: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ic1bd19087a4500ba0ca9e312ea351e301ab42518 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7301 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-07-18vendorcode/amd/agesa: Use macros already defined in stdlib.hEdward O'Callaghan
We already have these macros define in 'stdlib.h'. Make good use of them here to avoid redefinition conflicts of the pre-processor depending on header inclusion ordering. This has the nice side-effect of syncing up AGESA families in this particular regard. Change-Id: Icf911629a4a1a82b01062fe16af4c8f812b05717 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6199 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop whitespaces in .hEdward O'Callaghan
Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6189 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-10vendorcode/amd/agesa/f10: Trivial - drop trailing whitespacesEdward O'Callaghan
Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6185 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-21amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5801 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19amd/agesa: Implicit assigment between enum without castEdward O'Callaghan
Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.hEdward O'Callaghan
Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19vendorcode/amd: kill some intermediate variables in build systemPatrick Georgi
They don't exactly add clarity, but increase the risk they're used at some obscure place. Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5787 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19build: move include paths where they belongPatrick Georgi
They're _not_ part of the compiler binary, so they have no place in $(CC_*) Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-02vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.Edward O'Callaghan
A comparison with a two's complement in gcccar.inc has dubious GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal number. Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5277 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-04-16AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in commentsPaul Menzel
When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-08AGESA: Fix CR0_PE bit defineKonstantin Aladyshev
AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15Konstantin Aladyshev
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. EDX:EAX = MSR[ECX] So bit 49 will be contained in EDX register. Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis). PfcStrideDis bit disables stride prefetch generation. This leads to memory bandwidth loss. _________ Supermicro H8QGI board After applying this change i observed huge memory bandwidth increase in tests that runs on small amount of cores. But unfortunately it doesn't affect overall bandwidth results on 4P system with 48 cores. So i think that in this system leading limiting factor is AMD HT-ASSIST feature (Probe filter). But right now it is not working. System stucks in Linux boot. I have done some experiments and figured out that stuck happens when system have cores in compute unit (CU) other than CU with BSC (boot strap core). CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...) So with probe filter i can boot Linux with one (BSC) or two (BSC + secondary core in its CU) cores. And with this configuration i can see memory bandwidth on 1 core (or two cores) close to original bios. Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2588 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-01-02AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functionsAladyshev Konstantin
Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE". This results in a failure of init late function: "agesawrapper_amdinitlate failed: 1" It happens because TRUE = 1 = AGESA_UNSUPPORTED. Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem. Only family f15tn does not have such bug. This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family? Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15). Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2070 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-15Add the AMD Family10 Agesa codeefdesign98
This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/95 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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