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2015-06-04devicetree: Discriminate device ops scan_bus()Kyösti Mälkki
Use of scan_static_bus() and tree traversals is somewhat convoluted. Start cleaning this up by assigning each path type with separate static scan_bus() function. For ME, SMBus and LPC paths a bus cannot expose bridges, as those would add to the number of encountered PCI buses. Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8534 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19superio/nuvoton: Add support for Nuvoton NCT6779DMatt DeVillier
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10232 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-05-17nuvoton/nct6776: there is no IRQ for LDN8Felix Held
Change-Id: Ib4ee3633d210a05e06ed95fc13830cc692095501 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/10235 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-14superio: Replace the indexed I/O functionsDave Frodin
Replace the multiple indexed I/O read and write functions with common functions. Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10145 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-14superio/nct5104d: Handle shared GPIO/UART pinsKyösti Mälkki
Routing is decided based on enabled logical/virtual devices. For a valid devicetree, one should have only one of SP3 and GPIO0, and only one of SP4 and GPIO1, enabled at a time in configuration. Change-Id: I02017786aba9dd22d12403aaa71d7641f5bbf997 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14superio/nct5104d: Refactor IRQ trigger configKyösti Mälkki
That function was getting too long. Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10176 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-03-21superio: ite8772f: Exit extemp busy stateRyan Lin
It causes fan top speed due to this bug + our board-specific workaround, and causes invalid temperature sensor readings. Therefore, re-configure the register "External Temperature Sensor Host Control Register" to terminate processes when this issue happens. BUG=chromium:402204 TEST=ran suspend_stress_test 500 times Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9 Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219445 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/8820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-14superio/fintek/f81216h: Add the correct unlock key valuesDave Frodin
The actual key values were not added in commit 17ace8255. TEST: amd/lamar shows the correct result. Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8375 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: Marc Jones <marc.jones@se-eng.com>
2015-02-04superio/fintek: Add required changes so F81216H can be usedDave Frodin
The amd/lamar mainboard is the first mainboard to use the f81216h. These changes are needed to fix up commit 27a63d77 so the Super I/O builds and functions correctly. - Wrong #include name - Removed global variable in romstage - Missing "case" in switch() Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8255 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06superio: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the superio code to use printk() on all non-ROMCC boards. Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8113 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-06superio/smsc/lpc47n217: Drop dead codeStefan Reinauer
This code is unused, and the same functionality is in superiotool already. Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8112 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06superio/smsc/lpc47n207: Hook into build systemEdward O'Callaghan
Provide proper Makefile and Kconfig components so that this superio is built as object code. Select superio component in mainboard Kconfig's to bring in the link-time symbols and thereby removing the need for .c inclusion. N.B. The LPC47N207 Super I/O does not physically exist on these boards. The Super I/O is found on external LPC debug card hardware and so should really be made selectable. However, this is beyond the scope of this specific fix, that rids us of .c inclusions in romstage.c Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8084 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-04superio/smsc/lpc47b272/superio.c: Remove dead codeEdward O'Callaghan
Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8083 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04src/superio/smsc/lpc47m10x/superio.c: Remove dead codeEdward O'Callaghan
Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8082 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/smsc/lpc47b272: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: Id3d5f2a120c0a933c031102f206829305da20f0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8081 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/smsc/lpc47m10x: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: I4a3639c05231eacd016ec3873330f9844befd448 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8080 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/smsc/lpc47b397: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8079 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-04superio/nsc/pc87417: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8078 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-04superio/nsc/pc87366: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: Id156ca3c9a14c5bcc4d6cdb8434ca8efdac3139a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8077 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/nsc/pc97317: Use link-time symbols over .c inclusionEdward O'Callaghan
Change-Id: Ia45bc7a880d0dab57c56a0452858cd26626f09df Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8076 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/intel/i3100: Use link-time symbol over .c includesEdward O'Callaghan
Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8054 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04superio/nsc/pc87360: Use link-time symbol over .c includesEdward O'Callaghan
Change-Id: Id6d9efc93fdaff63dcaab50712ac9be35ccb42a7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8053 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-18Drop Intel E7520 and E7525 and related boardsStefan Reinauer
There is no Cache As Ram for these boards, let's get rid of them. Also drop unused dependencies Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7836 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-16Drop obsolete SuperIOs used by GX1 systems onlyStefan Reinauer
Drop two SuperIOs that were only used by GX1 systems, and are not used anymore. * winbond/w83977f * nsc/pc87351 Change-Id: I8a8eacb0f862b5d08ccfd87f8db503b0ab3c5700 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7118 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04superio/ite: Use common dispatch for pnp entry/exit functionsEdward O'Callaghan
We already have these implemented under superio/common, use those instead of this copy-paste syndrom. Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7310 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-01superio/fintek/f81216h: Implement device supportEdward O'Callaghan
Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7309 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO'sEdward O'Callaghan
Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-30superio/nuvoton: Add support for Nuvoton NCT6776Felix Held
Add support for both NCT6776D and NCT6776F devices. Change-Id: If6686ea0a1cd6be537e286699b4ee8f88ba8ad7c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/5450 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-30superio/nuvoton: Add support for Nuvoton NCT5572DFelix Held
Change-Id: I3b720cf879bf5326be885d2d3a3f9cfba0a27c7e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6229 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins)
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins)
2014-10-27superio/*/superio.c: Don't hide pointer types behind typedefsEdward O'Callaghan
Hiding pointer types behind 'typedef's is usually not a great idea at the best of times. Worse the typedef becomes an integer at different stages in Coreboot. Let us refrain from doing this at all. Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7136 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-27superio: Use 'pnp_devfn_t' over 'device_t' in romstage componentEdward O'Callaghan
The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. This follows on from the rational given in: c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6231 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-10-27superio/common/conf_mode.c: Don't hide pointers with typedefsEdward O'Callaghan
Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2014-09-17pnp: Allow setting of misc register 0xf4 in device treeStefan Reinauer
Change-Id: I602f970e0ee2fd634a74fd4c25358c2e78ca58f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/179536 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 02b0583e632f1ba53557f8cfe4293ad4ed29ff4d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6910 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-11pnp: Allow setting of misc register 0xfa in device treeStefan Reinauer
Change-Id: I45885905f0adaa8f0ad9137d7034e6f7a0dc43de Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/175356 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 7fe642543a8de249e13c3d63c3302a20910c247d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6859 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-23superio/smsc/sch4037: Cleanup and fix .c inclusionEdward O'Callaghan
Clean up both ram and rom stage support and fix board to match. Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6509 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-08-23superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c includeEdward O'Callaghan
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6463 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-08-09superio/smsc/sio1036: Clean up RAMstage superio.c componentEdward O'Callaghan
Remove spurious includes, unused variables and some wasted new lines. Re-organise things to be consistent with other superio's. Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6465 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-18superio/f71869ad: fix documentation of io_info mask valuesFelix Held
Change-Id: I5d0a945de45f8f4a77193135e63f480af14a0136 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6279 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-18src/superio/smsc/lpc47m15x: Avoid #include early_serial.cEdward O'Callaghan
Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18superio/smsc: Add some missing header guardsEdward O'Callaghan
Change-Id: Id3f85929024208b150c378d7636607a0c9b8617c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6302 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-18src/superio/ite/it8772f: Separate mainboard from SIO at obj levelEdward O'Callaghan
Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17superio,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ia452e22af9491c1681c859691eb4ac1868eeb938 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6282 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-15superio/fintek/f71869ad: config struct should be const qualifiedEdward O'Callaghan
The 'superio_fintek_f71869ad_config' struct packed by devicetree.cb should have its type declared with the 'const' qualifier. Change-Id: Ieb86861ee821e77680cc4d0de202dbd7535b844d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6224 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-08superio: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I8633d331d095fe9506a8f01969060ba9889c8eac Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6202 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-21PS2 keyboard: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6073 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21superio/smsc/fdc37n972: Trivial cleanup reorder headersEdward O'Callaghan
Alphabetise headers and a few trivial cleanups. Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6042 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20superio/nuvoton: Add chip support for setting IRQs to edge/levelDave Frodin
Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/6064 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-20superio/nuvoton: Adds a function to route pins 41-48 to UARTDDave Frodin
Pins 41-48 default to being GPIs. This switches the internal mux to connect them to UARTD. Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20superio/ite/it8772f: Remove prototypes for func with no bodyEdward O'Callaghan
Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-12superio/smscsuperio: Fix chip detectionKyösti Mälkki
There was dereference of NULL dev->ops in pnp_enter/exit_conf_mode() as those calls were made before pnp_enable_devices() was run. Since hardware did not enter configuration mode, detection failed with ID and REV read as 0xff. Change-Id: If13086707cd86e392890ccf4f717e13a87f3317f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5949 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-06-09nuvoton/nct5104d: Update the #defined LDNsDave Frodin
Change-Id: I4e4bc09a8f8fabe68519a29dc421af82c76c9873 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5944 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-06superio/nuvoton: factor out generic romstage componentsFelix Held
The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips) is identical, so the early_serial.c file can be moved under nuvoton/common. The Nuvoton BMC chip WPCM450 is however left untouched. Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/5909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-06superio/smsc/kbc1100: Virtually rewrite support and fix mainboardsEdward O'Callaghan
1. Remove #include .c in romstage. 2. Make romstage component symbols linker-time. 3. Provide header guards and prototypes in superio romstage support. 4. Correct function type-signatures to be static/non-static where appropriate, avoid 'pretend optimisations' by unnecessarily inlining functions. 5. Separate out UART enable from various other PNP hard coding Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5916 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03superio/smsc/smscsuperio: Make romstage linkable with headerEdward O'Callaghan
Rewrite smsc/smscsuperio romstage component to be more consistent and provide header there-by removing #include's of early_serial.c's in mainboard's. Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5915 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03superio/ite/it8661f: Make early_serial into romstage symEdward O'Callaghan
Following similar reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Avoid any mistaken future inclusion of early_serial.c in mainboard.c code by providing symbols in romstage. Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5508 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03superio/ite/it8772f: Depreciate early wdt functionsEdward O'Callaghan
We have better written generic implementations of these functions introduced in commit: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5901 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03superio/ite/it8772f: Move towards removing #include .cEdward O'Callaghan
Move samsung/stumpy board towards generic romstage component and away from poorly written hard-coded model specific Super I/O component. This is an incremental step towards getting obj-level abstraction between board and Super I/O. Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5899 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31superio/nsc/pc87309: Avoid .c includes in mainboardEdward O'Callaghan
Make superio romstage component link-time symbols. Change-Id: Icde27465a05946498ff7b8f1aaa7a9e8ba074272 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5880 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31superio/winbond/w83627hf: Avoid .c includes in mainboardsEdward O'Callaghan
Move towards the removal of the superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable(). Special cases: - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func Provide local superio pnp_ programming entry/exit functions as to avoid making superio implementation global symbols. Although this is not the proper/final solution, it does mitigate possible symbol collisions and allow for continued superio refactorisation. Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5601 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31superio/winbond/w83627ehg: Depreciate romstage componentEdward O'Callaghan
Part 1/2: These are actually not necessary if Super I/O support is properly utilized. Change-Id: I39b621e582f8d0762276d29492c91dce500f0665 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5870 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-28superio/winbond/w83627thg: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5724 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28superio/winbond/w83627uhg: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Convert dependent board to generic winbond serial init. Note the clock function is actually invalid since it never enters into PNP config mode to twiddle the register. Further, 48MHz is the default (page 9 of data-sheet) and so romstage.c need not do anything to the clock rate hence why it presumably works with this invalid function. Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5725 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28superio/ite/it8712f: Depreciate model specific early_serial.cEdward O'Callaghan
We now have common ite_*_*() functions for romstage and hence no longer require the model specific portion of this superio support. Change-Id: I30400abf27008a88072673075bba445f100d9ad3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5838 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28superio/ite/it8712f: Drop model specific sio func for generic verEdward O'Callaghan
Drop it8712f_kill_watchdog() in favor of common ite_kill_watchdog() introduced in commit rev: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I9fc4d3ee7992618b5b14e35166e848d6e1cffa8b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5837 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-24superio/ite/it8721f: Trivial drop redundant headersEdward O'Callaghan
Change-Id: Ib086cd567c926dd659f67900195f93262ceb50c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5839 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-23superio/winbond/w83697hf: Depreciate romstage componentEdward O'Callaghan
Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-23Implement proper IT8728F PNP opsRudolf Marek
The Asus F2A85-M has IT8306E which is a stripped down version of this SIO. Implement the PNP operations of the SIO. Change-Id: Ibc4f3fafc3ffb1cd799948e63be01e6924b45d6c Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/4498 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23ite/common: Introduce common watchdog and 3.3V VSB helpersRudolf Marek
Introduce the watchog and 3.3 VSB helper functions. The IT8712F can be migrated to use those too. To be used with IT8728F. Change-Id: If21e99b6069c7222f0bc8eb7c7121fe119b8dfe1 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/5728 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23superio/ite/it8728f/it8728f_hwm.c: Small fixesRudolf Marek
Use proper include header in it8728f_hwm.c, fix format error. The base of HWM block starts at offset +5. Change-Id: I6855225b38bbcf5687d506bea9482c951d314684 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/5729 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-05-13src/*: Remove the last remnants of struct keyboardEdward O'Callaghan
Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5624 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Remove redundant chip.h headerEdward O'Callaghan
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5622 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13superio/*: Deal with some chip.h special casesEdward O'Callaghan
While backing out the empty pc80 keyboard struct we encountered some special cases where chip.h is used for other purposes. Deal with these cases. Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5621 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-12superio/ite/it8718f: Remove hard coding from romstageEdward O'Callaghan
Make use of the ITE common Super I/O framework and there-by removing any hard coding of Super I/O base address. Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5717 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-11superio/ite/*: Factor out generic romstage componentEdward O'Callaghan
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5585 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11superio/ite/it8728f: RAMstage PNP configuration componentEdward O'Callaghan
Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5668 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-10superio/fintek/f71869ad: Fix incorrect LDN'sEdward O'Callaghan
Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc. Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5696 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09superio/serverengines/pilot: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08superio/fintek/f71869ad: Make hwm devicetree configurableEdward O'Callaghan
Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5580 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08superio/fintek/f71869ad: Configure multi-func reg in devicetreeEdward O'Callaghan
Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07superio/common/conf_mode: Provide another common pnp entry/exitEdward O'Callaghan
ITE Super I/O's make use of this method to enter and exit in and out of their PNP configuration. Provide functions for use in ram stage component. Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5666 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-06Introduce stage-specific architecture for corebootFurquan Shaikh
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-02superio/winbond/w83627thg: Remove w83627thg_enable_serial symbolEdward O'Callaghan
Remove model specific implementation, w83627thg_enable_serial, from romstage component of sio support. Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5604 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627ehg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627dhg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/*: Provide common romstage componentEdward O'Callaghan
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5587 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26superio/fintek/*: Factor out generic romstage componentEdward O'Callaghan
The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/fintek/*: Fix header styleEdward O'Callaghan
Remove some redundant includes. Fix repetitiveness in include guards and strip some misplaced tabs for whitespaces. Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5572 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8673f: Remove poor implementationEdward O'Callaghan
Following the reasoning of: HASH superio/ite/it8705f: Remove poor implementation Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5568 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8705f: Remove poor implementationEdward O'Callaghan
This super io support is poorly implemented and would not work for all boards since it hardcodes values. Since there are no users of it, remove for now pending a fresh reimplementation from scratch. Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5566 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8716f: Rewrite from hardcoded base addrEdward O'Callaghan
Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8721f: Rewrite from hardcoded base addrEdward O'Callaghan
Rewrite early_serial.c implementation to honour a passed base address in device_t, removing any hard coding of values. We also expose early sio init functions as romstage symbols to avoid falsely #including "early_serial.c" in romstage.c of board support. Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-15superio/ite/it8728f: Fix headers and prototype locationEdward O'Callaghan
Try to conform to some kind of standard/consensus for prototype location. Correct headers while here. Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5499 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/winbond/w83627thg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/nuvoton/nct5104d: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5446 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>