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2020-05-11superio/winbond/w83977tf: Only list IR logical device if neededKeith Hui
Really old versions of W83977TF Super I/O had an IR logical device, but is no longer the case. It does not exist in the newer W83977EF version, installed in some Asus P2B family boards, and served by this same code. Add a config option on the off chance we may see board with it (as if we would) and don't include this device unless it is set. Saves us from the need to declare a not-present device off and/or extraneous PNP device errors about a not-present device. Change-Id: I761ebc41f1735a03e768339a68ca139167edc095 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41004 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05superio/fintek/f81216h: Drop supportKeith Hui
No mainboards use this anymore. Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-29superio/aspeed/common: Add early configure functionsBryantOu
Add LPC read/write functions for access aspeed's memory, also create config data table to config memory and SIO. These functions are used at early stages to configure devices. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/fintek: Improve code formattingElyes HAOUAS
Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/{acpi,common}: Improve code formattingElyes HAOUAS
Change-Id: I879ac7b558781d559a65c97fc8b914ecc4ad3f0d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/ite: Improve code formattingElyes HAOUAS
Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/nuvoton: Improve code formattingElyes HAOUAS
Change-Id: I8cdfa5c3e3508ea8ad969df6513401611a066fc5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39930 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31superio/winbond: Improve code formattingElyes HAOUAS
Change-Id: Ia63e21b957d89690f36929f9ffbe8a7bf8f0e84c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/smsc: Improve code formattingElyes HAOUAS
Change-Id: Ia9a3f7795178400de39b36471f4169a9f5a3b08b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31superio/winbond/{w83627hf,w83977tf}: Use macroElyes HAOUAS
Change-Id: I3ac8dd2ba089970a18b460769dfc3fabf9395709 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39907 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29superio: Replace D1/D2 power states with D3Nico Huber
Spec says if any object to control the power state exists, at least D0 and D3 must be supported. And it seems Windows complains about the missing D3 support: https://ticket.coreboot.org/issues/257 Windows reported `*** STOP: 0x000000A5` with the first parameter `0x000000000000000D` (refers to a missing ACPI object) and the third parameter `0x000000003353505F` which is the name of the object in ASCII, little-endian (`_PS3`). Change-Id: Ifa28a7c56575848e76e4a1c542866413b4c44d50 Signed-off-by: Nico Huber <nico.h@gmx.de> Closes: https://ticket.coreboot.org/issues/257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25create stdio.h and stdarg.h for {,v}snprintfJoel Kitching
Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create stdio.h and stdarg.h header files. Relocate snprintf into stdio.h and vsnprintf into stdarg.h from string.h. Chain include these header files from string.h, since coreboot doesn't care so much about the legacy POSIX location of these functions. Also move va_* definitions from vtxprintf.h into stdarg.h where they belong (in POSIX). Just use our own definitions regardless of GCC or LLVM. Add string.h header to a few C files which should have had it in the first place. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-25superio/nuvoton/nct5104d: add chip config option to reset GPIOsMichał Żygowski
Define a chip option to explicitly soft reset all enabled GPIOs to default state. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-11superio/nuvoton/nct5539d: Update documentation and remove DSDTPatrick Rudolph
There seems to be no board using this, but some currently under review. Remove the DSDT, which doesn't work together with the SSDT ACPI code generation. Also update the documentation pointing to the SSDT generator. Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-10winbond/w83667hg-a: Disable mouse controller also during resumePaul Menzel
There is no reason to not disable the controller during resume. That way, no ASL is needed. Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02superio/nuvoton/npcd378: Switch to superio/commonPatrick Rudolph
Replace DSDT ACPI code and DSDT injection with a SSDT only solution. The current implementation shows some issues on current Linux, which might be due to external ACPI objects, which are then injected into DSDT or the fact that those objects only use 3 characters. Replace all the DSDT code with an SSDT generator. Tested on HP Z220: Boots into Linux with no ACPI errors. The SSDT can be disassembled. Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-28superio/common: Validate devicetreePatrick Rudolph
As the SSDT generator for LDNs expects a "parent" PNP device for proper ACPI code generation, validate that it is present. Make sure the devicetree looks as expected and print a BUG message if that's not the case. Tested on HP Z220: No BUG message was printed. Change-Id: I6cbcba8ac86a2a837e23055fdd7e529f9b3277a2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-25superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHBMichael Niewöhner
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-25superio/aspeed/ast2400: rename SWAK to SWC to match the datasheetMichael Niewöhner
The datasheet uses "SWC" as shortcut for "System Wake-up Controller", thus rename it in the code. Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-09superio/nuvoton/nct5539d/acpi: fix # comment in superio.aslPavel Sayekat
Change-Id: Ic2ba1f9b744014f97d318671bf86468f4d6c6469 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-30src/superio/*: Fix typosPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find src/superio -name '*.[ch]') Change-Id: I36fd8cfeffdaf81d7ac646bab7ffac3e36c77879 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30src/superio: replace license boilerplate with SPDXFelix Held
The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-26superio/aspeed/ast2400: Fix Register OffsetChristian Walter
According to the specification the register offset must be 0x71 instead of 0x70. Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-20superio/nuvoton/nct5104d: Add virtual LDN for simple GPIO IO controlPiotr Kleinschmidt
Now, Super I/O GPIOs can also be controlled directly through access to I/O registers. VLDN 108 and specific I/O port from a range <100h; ff8h> may be enabled in mainboard devicetree. Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15superio/nuvoton/nct5104d: Add soft reset GPIO functionalityPiotr Kleinschmidt
So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOs are not in unknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09acpi: Be more ACPI compliant when generating _UIDPatrick Rudolph
* Add function to generate unique _UID using CRC32 * Add function to write the _UID based on a device's ACPI path ACPI devices that have the same _HID must use different _UID. Linux doesn't care about _UID if it's not used. Windows 10 verifies the ACPI code on boot and BSODs if two devices with the same _HID share the same _UID. Fixes BSOD seen on Windows 10. Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09superio/common/ssdt: Make disabled PNP devices ACPI compliantPatrick Rudolph
Always write a _HID, even for disabled PNP devices. Fixes a BSOD on Windows 10. Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-12-31src: Remove some romcc workaroundsJacob Garber
Now that romcc is gone, move cmos_post_init() into post.c, and remove some preprocessor workarounds. Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-30superio/nuvoton: add common HWM bank select functionFelix Held
Change-Id: I828b6caa37e52c13e1876c7ca4edbd171e70d3f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37945 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-22superio/common: Add more ACPI methodsPatrick Rudolph
* Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-22superio/common/conf_mode: Add op to write SSDTPatrick Rudolph
Add functions to write ACPI SSDT code for entering and leaving the config mode. To be used by ACPI generators. Tested on Linux 5.2 using the Aspeed SSDT generator. Change-Id: I14b55b885f1c384536bafafed39ad399639868e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-20superio/smsc/lpc47m10x: Expose pnp_enter/exit_conf_stateKyösti Mälkki
Change-Id: I55915b63dbb097634a228193f62395e45a1f42fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-17superio/aspeed/ast2400: Add AST2500 supportPatrick Rudolph
The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-16device/pnp: introduce and use PNP_SKIP_FUNCTIONFelix Held
-1 shouldn't be assigned to an unsigned variable, so use an otherwise unused constant here. Since 7 is the highest virtual LDN number, using 0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects. Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-16superio/ite/it8728f: remove unused LDN selection register defineFelix Held
Change-Id: Ie7a8af46a59c36b0dd62f227a6b53918c8fde7b8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37742 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16superio/ite: remove unused stdint.h include from header filesFelix Held
Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-15mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state functionElyes HAOUAS
Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13superio/*: Don't use conf_mode directlyPatrick Rudolph
Use the functions defined in device/pnp.h instead of using the conf_mode directly. This will make future refactoring easier. Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-12superio/common/generic: Assign resources behind deviceChristian Walter
If multiple devices are behind a dev, we would only recognise port 0. We need to scan the complete 'bus'. Tested on ASpeed AST2500 Change-Id: Id80a2ae6e82c151b8d8adc9c5f35f38362d538fa Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37607 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-06src/superio: Remove unused intel's superio chipsElyes HAOUAS
Change-Id: Ie693ff700a804778682daf0cb3990a56ab747a93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-06superio/smsc/lpc47n207: Remove unused <stdint.h>Elyes HAOUAS
Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-06superio/nsc/pc87417: Remove unused <stdint.h>Elyes HAOUAS
Change-Id: Icacf2806702a868a807080e1e2d14b1ee4ed4f90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37507 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-06src/superio/via: Remove unused superio chipsElyes HAOUAS
Change-Id: I248608361fcdc51ff435222d37c5bbc736b1947e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-06superio/fintek: Fix typoElyes HAOUAS
Change-Id: If5c0921e20b26ce558f542f405cf62ae8d4a8101 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-05superio/fintek/f81866d: capitalize 'TODO'Elyes HAOUAS
Change-Id: I2879a8739012863837e23e60fed5eb6ee209dea0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/serverengines/pilot: Fix typoElyes HAOUAS
Change-Id: Ic7cd93150252b2e5235c82c8c63540059b68d22b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/smsc/lpc47n2{17,27}: Fix typoElyes HAOUAS
Change-Id: I29a42908af5699200216b7a0082e1417c90c95a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/ite/it8528e: Fix typoElyes HAOUAS
Change-Id: I40035bf622fea2ff7aed74dce125cbf6265afa6e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-05superio/{aspeed,nuvoton}: Fix typoElyes HAOUAS
Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-02superio/aspeed: Remove unused aspeed include pathMartin Roth
Working on some other code, I noticed that superio/aspeed was added as an include path even though I wasn't using it. I investigated and found that NOTHING is using it. The files in the aspeed directory all reference files in their own directory. The supermicro x11-lga1151-series boards are the only ones using this SIO. TEST=util/abuild/abuild -t supermicro/x11-lga1151-series Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-01src/superio: Remove unused include <stdlib.h>Elyes HAOUAS
Change-Id: I941c3d80d6b822b12a2d0c279415ab0c6b7f375b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-01superio/nct5539d: include the missing acpi.h and ssdt.hMaxim Polyakov
Change-Id: Idd80fae1c39f3c7c4bc66a42e9023fb7a727b024 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-05superio/*/*/acpi: Improve the readability of the IndexFieldElyes HAOUAS
Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04superio/nuvoton/nct5539d: use SuperIO ACPI generatorMaxim Polyakov
Adds SuperIO SSDT ACPI generator[1] support. Not tested on real hardware. [1] https://review.coreboot.org/c/coreboot/+/33033 Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04superio/nuvoton/nct6791d: use SuperIO ACPI generatorMaxim Polyakov
Adds SuperIO SSDT ACPI generator[1] support. It has been tested on Asrock H110M DVS motherboard [2]. [1] https://review.coreboot.org/c/coreboot/+/33033 [2] https://review.coreboot.org/c/coreboot/+/36381 Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04superio/aspeed/common: add workaround for serial routing delay quirkMichael Niewöhner
Some mainboards with an ASPEED BMC do the serial routing setup in the BMC boot phase on cold boot. This results in scrambled console output when this is not finished fast enough. This adds a delay of 500ms as workaround in the BMCs uart setup that can be selected at mainboard level. A user may disable the workaround when using another BMC firmware like OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup. Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-20src: Remove unused 'include <string.h>'Elyes HAOUAS
Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20superio: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: I55e7b680e128f29a9fd549edfb676e6571330677 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20superio: Remove unused include <device/smbus.h>Elyes HAOUAS
Change-Id: Ic8a28493c386c0097dbf3478e6d046fdfbf28724 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-18superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.aslPavel Sayekat
This port is based on NCT6776 Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18superio/smsc: Restore sio1036Marshall Dawson
Change d3a1a417 "src/superio: Remove unused superio chips" removed all unused devices except for ones used on mainboards still under review. The SMSC 1036 was inadvertenly also removed as well. This device is used in debug cards that may be connected to AMD CRBs. This patch restores the smsc1036 directory as-is and then corrects the following lint messages. * WARNING: Prefer 'unsigned int' to bare use of 'unsigned' * ERROR: else should follow close brace '}' * WARNING: braces {} are not necessary for single statement blocks Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16src/superio: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-13src/superio: Remove unused superio chipsMartin Roth
These SIOs are not being used or tested by abuild, so remove them from the tree. The only 3 currently unused SIOs that don't get removed here have board ports in review. src/superio/fintek/f71805f src/superio/fintek/f71872 src/superio/intel/i8900 src/superio/ite/it8671f src/superio/ite/it8716f src/superio/nsc/pc87309 src/superio/nsc/pc87360 src/superio/nsc/pc87366 src/superio/nsc/pc97317 src/superio/smsc/dme1737 src/superio/smsc/lpc47b272 src/superio/smsc/lpc47b397 src/superio/smsc/sch4037 src/superio/smsc/sio1036 src/superio/via/vt1211 src/superio/winbond/w83697hf src/superio/winbond/wpcd376i Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-13superio/common: Remove unused include 'pnp_def.h'Elyes HAOUAS
Change-Id: I2d0b3d73d646fc43f2562aa5af2358398eaf28b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-08superio/it8772f: use pnp_ops.h for pnp register accessFelix Held
Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/winbond/w83627*: use hwm5_conf.h for HWM setupFelix Held
Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/it8772f: use HWM access functionality from hwm5_conf.hFelix Held
Change-Id: I12ac8dd0503f3c46fdb50e49df60c01387128b55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-08superio/hwm5_conf: factor out HWM access from ITE env_ctrlFelix Held
Nuvoton and Winbond use the same off-by-5 indirect address space to access their hardware monitor/environment controller in the SIO chip, so move this to a common location and replace the inb/outb calls with the corresponding inline functions from device/pnp.h Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07src: Capitalize Super I/OElyes HAOUAS
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-07device: Rename scan_static_bus() -> enable_static_devices()Nico Huber
The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17superio/common: Fix types in printfPatrick Georgi
Found by Coverity Scan #1405310 Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35433 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11superio/common: fix regression in ssdtMichael Niewöhner
ITR2 is specified twice here, which leads to the following error message in Linux: [ 0.263591] ACPI BIOS Error (bug): Failure creating named object [\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633) Add comments and fix duplicated field. As there are no users of this code yet, just rename the fields. Tested on Supermicro X11SSH-TF. Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35294 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06superio/smsc/lpc47b397: fix regression in ops overrideFelix Held
b0d868e8fe3f9a13f9be109fc3b73dfa949bec15 introduced a regression Change-Id: I231888f2702027a80f25eb418c4e4703e55db920 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marcello Sylvester Bauer <sylvblck@sylv.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-06src/superio/aspeed/ast2400: Use new SuperIO acpigenChristian Walter
Use the new SuperIO ACPI generator to make includes in DSDT obsolete. Manually tested on X11SSH-TF and verified that ACPI tables are correct. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06superio/common: Add ssdtgen for generic SuperIOsPatrick Rudolph
Add a generic SuperIO ACPI generator, dropping the need to include additional code in DSDT for SuperIO. It generates a device HID based on the decoded I/O range. Tested on Supermicro X11SSH-TF using AST2400. The SSDT contains no errors and all devices are present. Possible TODOs: * Add "enter config" and "exit config" bytes * Generate support methods to enter and exit config mode * Generate support methods to query, change or disable current resource settings on specific LDNs Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-08-27smsc/superio/sio1007: Fix header nameKyösti Mälkki
The file chip.h has a special purpose for defining the configuration structure used in static devicetree. Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29src/superio/nuvoton: Add support for NCT5539DPavel Sayekat
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-26superio/fintek: Add f81803ARichard Spiegel
Add f81803A plus the capability to control the fan with any fintek SIO. This will be done through a common API, though currently only F81803A will have it implemented. BUG=none. TEST=Tested later with padmelon board. Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-22nuvoton/early_serial: improve comments on serial pinmux settingsFelix Held
Change-Id: I36c0d752df97810bd99d2eec27403545421ce533 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21superio/nuvoton/nct6776: Make Kconfig symbol dependentAngel Pons
The SUPERIO_NUVOTON_NCT6776_COM_A symbol should only be visible if SUPERIO_NUVOTON_NCT6776 is selected as well. Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33440 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21superio/nuvoton/nct6791d: Add symbol to select COM portAngel Pons
Like the NCT6776, the NCT6791D has muxed COMA/GPIO8 functions. Since it requires setting different bits, add a new Kconfig symbol to do it. Change-Id: I62dc18810026f9b1550da19950f66af605600ec8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-25superio/fintek/f71863fg: Remove variable set but not usedElyes HAOUAS
Change-Id: I993055d237b2bd607822485d34d5508c74a7744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-24superio: Add ASpeed AST2400Frans Hendriks
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-15superio/ite: Add IT8786E-IKyösti Mälkki
Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-15src/superio/ite/common: Prepare for ITE IT8786E SuperIOMichał Żygowski
Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous 7bit values for PWM slope. Add option to enable External Sensor SMBus Host. Update/add registers macros for IT8786E-F which are not backwards compatible. Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-01superio/fintek/f71808a: Add more optional ramstage registersMax Blau
Add more registers and make them optional, so they keep untouched/ their default if omitted. Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-18src/nsc/common/nsc.h: Drop unused includeElyes HAOUAS
Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-14Remove leftover filesKyösti Mälkki
Change-Id: I7fa27a2cbc73b4acae41373a51f600f32b9002bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06superio/ite/it8613e: add support for ITE IT8613EKrystian Hebel
This change adds support for the SuperIO chip IT8613E. This chip uses FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so it relies on support in common ITE code. LDNs were taken from IT8613E Preliminary Specification V0.3. Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04device/pnp: Add header files for PNP opsKyösti Mälkki
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31698 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 15:46:54 +0000