| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-04-20 | pci1x2x: remove latency/bridge control/cacheline size settings | Sven Schnelle |
| 2011-04-20 | pci1x2x: use devicetree register configuration | Sven Schnelle |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |