| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-01-14 | sb/intel: Use common RCBA MACROs | Peter Lemenkov |
| 2019-01-09 | cpu/intel: Use the common code to initialize the romstage timestamps | Arthur Heymans |
| 2017-11-23 | sb/intel/i82801ix: fetch initial timestamp in bootblock | Arthur Heymans |
| 2016-09-13 | southbridge/intel/i82801ix: transition away from device_t | Antonello Dettori |
| 2016-01-07 | Correct some common spelling mistakes | Martin Roth |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-02-15 | x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer | Kevin Paul Herbert |
| 2014-07-08 | southbridge: Trivial - drop trailing blank lines at EOF | Edward O'Callaghan |
| 2013-03-22 | x86: Unify arch/io.h and arch/romcc_io.h | Stefan Reinauer |
| 2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
| 2012-11-27 | intel/i82801ix: new southbridge, ICH9 | Patrick Georgi |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |