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path: root/src/southbridge/intel/i82371eb/i82371eb.h
AgeCommit message (Expand)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-01-14sb/intel/i82371eb: Add PIIX4 definitionsKeith Hui
2020-01-14sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki
2020-01-12asus/{p2b-x,p3b-f},intel/i440bx: Move mainboard_romstage_entry()Kyösti Mälkki
2020-01-02intel/i82371eb: Drop unused codeKyösti Mälkki
2019-12-14sb/intel/*: Remove romcc guardsArthur Heymans
2019-08-21southbridge/intel: Tidy up preprocessor and headersKyösti Mälkki
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2018-05-14sb/intel/i82371eb: Get rid of device_tElyes HAOUAS
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
2013-05-10Drop prototype guarding for romccStefan Reinauer
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
2010-11-29Tobias Diedrich wrote:Tobias Diedrich
2010-11-27After finding the missing bit poweroff works now.Tobias Diedrich
2010-10-09Remove various .c #includes from Intel 440BX/82371EB boards.Uwe Hermann
2010-09-19Make ASUS P3B-F RAM init actually work by enabling SPD access.Uwe Hermann
2010-03-28drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking...Stefan Reinauer
2009-11-06Split the two usages of __ROMCC__:Myles Watson
2009-10-27Add few missing prototypes, and remove few unused (thus lonelly) variables.Maciej Pijanka
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
2007-11-30Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):Uwe Hermann
2007-06-03Intel 82371EB: Some code simplifications (trivial).Uwe Hermann
2007-05-29Intel 82371EB: Add IDE init support.Uwe Hermann
2007-05-27Init for the Intel 82371EB southbridge: make all ROM/BIOS regionsUwe Hermann
2007-05-03Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,Uwe Hermann