coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-11-04	sb/intel: Use defined CONFIG_HPET_ADDRESS	Elyes HAOUAS
2019-11-04	sb/intel: Move 'smbus.asl' to common place	Elyes HAOUAS
2019-11-01	soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpi	Subrata Banik
2019-01-07	sb/intel/fsp_rangeley: Fix typo in GPIO Level	Elyes HAOUAS
2018-06-14	src: Get rid of unneeded whitespace	Elyes HAOUAS
2018-05-09	src/southbridge: Serialize methods with named objects inside	Martin Roth
2016-08-01	Remove non-ascii & unprintable characters	Martin Roth
2015-12-06	intel/fsp_rangeley: change non-existent config options to #defines	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-14	Revert "Remove FSP Rangeley SOC and mohonpeak board support"	Martin Roth
2015-10-03	Remove FSP Rangeley SOC and mohonpeak board support	Alexandru Gagniuc
2015-05-21	Kill ENABLE_TPM.	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-25	intel: Remove IRQ1 from possible PIRQ assignemnt.	Vladimir Serbinenko
2014-11-08	fsp_rangeley: Switch to per-device ACPI	Vladimir Serbinenko
2014-08-18	southbridge/intel/fsp_rangeley: fix to include irqroute.h twice	Martin Roth
2014-07-30	southbridge/intel: Add fsp_rangeley support	Martin Roth