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2015-03-11x86 SMM: Replace weak prototypes with weak function stubKyösti Mälkki
Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-01-06southbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the southbridge code to use printk() on all non-ROMCC boards. Change-Id: I312406257e66bbdc3940e206b5256460559a2c98 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8110 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2015-01-05timestamps: Switch from tsc_t to uint64_tStefan Reinauer
Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8020 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-04smihandler.c: Fix doxygen errors in southbridge_smi_handlerMartin Roth
Correct the param to match the functions. Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8074 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30Intel FSP: Fix GPI status outputKyösti Mälkki
Propagate commit 07c3fc089 to Intel FSP. Change-Id: Ie3e05df7fc06cb0ed6142edfedafab0cde74a68c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7966 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
According to spec IRQ1 isn't available for PIRQ assignment. Has gone unnoticed probably because modern OS use MSI or at least APIC and even with noapic don't use IRQ1 with PCI IRQs. Change-Id: Idc7db249007df629b27e8cae41cc80358d5306f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7478 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09ibexpeak, bd82x6x: Move to implicit length patchingVladimir Serbinenko
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-08bd82x6x: Move to common FADT.Vladimir Serbinenko
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-05soutbridge/*/bootblock: Use pci_dev_t over device_t typedefEdward O'Callaghan
Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7193 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
Most of the code related to the mc146818 is not related to the RTC and is really for managing the CMOS storage. Since we intend to add a generic API for RTC drivers it's inconvenient for those functions to have an rtc_ prefix. This CL renames those functions so they start with cmos_ instead. There are some places where rtc_init was called with a comment that says something about starting the RTC. That wasn't correct before (the RTC is always running), but it looks a little odd now that the function is called cmos_init. This CL also opportunistically cleans up some style problems in this file. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/197794 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788) Removed the addition of stdint.h to mc146818rtc.h since types.h is now included. Changed rtc_init to cmos_init for fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex. Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18fsp_sandybridge: Move to per-device ACPI.Vladimir Serbinenko
Just took combined sandybridge per-device ACPI patch and applied it on FSP flavour to avoid need of separate tests. Change-Id: I09838cc01ede504416078edcb1c267a11539e714 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-08-10intel/fsp_bd82x6x: Fix cycle error some morePatrick Georgi
As a follow up to #6479 (63e1948643fcbd763c83b6baa6cd9a077d49f1fc), fix the remaining faulty loop. Change-Id: I2c77efe620c71e939f4d74e48f90a166c782e5f5 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6569 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-03intel/fsp_bd82x6x: Fix cycle errorPatrick Georgi
Some copy-pasta snuck in that reintroduced an error already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071) Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I8ef5f1571ad14ead2d4cc0d61b6b7133d7fc8550 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6293 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-08southbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6209 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-21intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-18ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-04-11intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03Paul Menzel
GP0e does not fit into the naming scheme of the field units surrounding this field unit definition. Also the keys for e and 3 are close to each other supporting the theory that this is indeed a typo. Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31 Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5483 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04bd82x6x, ibexpeak, lynxpoint: Unify SPI.Vladimir Serbinenko
SPI registers didnt change since ICH8. No need to have separate files for them. Unify. Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5254 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-16usbdebug: Remove EHCI_DEBUG_OFFSETKyösti Mälkki
Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-05intel/fsp_bd82x6x: Use correct type pointer for mainboard_smi_gpiAlexandru Gagniuc
mainboard_smi_gpi has recently been updated to take a u32 argument from a u16, but the patch introducing the fsp_bd82x6x support has been verified on a master before this change, thus resulting in a 'cast from incompatible type' error. Update the pointer to the correct size argument. Change-Id: I9d62ee43f7c8ed774898f54d29a87cf463b76e91 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-04Add Intel FSP bd82x6x southbridge supportMarc Jones
Add support for the bd82x6x using the Intel FSP. The FSP is different enough to warrant its own source files for now. The mrc/system agent chromebook solution does much more southbridge initialization and configuration than the FSP version. It may be combined in the future. Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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