diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-19 19:50:51 +0300 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-06-21 08:04:52 +0200 |
| commit | c3ed88636a3533b97cef5bcb445cbe61edbfae7f (patch) | |
| tree | 12b51d3abb1876d41a8fd1b2bcf899e316b3d511 /src/southbridge/intel/fsp_bd82x6x | |
| parent | 49380b87d114cf4c1bd6f0692f43e89e73f662b8 (diff) | |
intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/elog.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/me.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 5 |
4 files changed, 4 insertions, 10 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/elog.c b/src/southbridge/intel/fsp_bd82x6x/elog.c index 09dfcdbc2c..55fe06f45b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/elog.c +++ b/src/southbridge/intel/fsp_bd82x6x/elog.c @@ -80,7 +80,7 @@ void pch_log_state(void) /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_slp_type == 3 ? 3 : 5); + acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 2633a49836..4351e001a3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -406,7 +406,7 @@ static void pch_lock_smm(struct device *dev) u8 reg8; #endif - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(0xe1, 0xb2); // Enable ACPI mode diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index c61d12b7c9..2282378997 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -553,12 +553,9 @@ static me_bios_path intel_me_path(device_t dev) struct me_hfs hfs; struct me_gmes gmes; -#if CONFIG_HAVE_ACPI_RESUME /* S3 wake skips all MKHI messages */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) return ME_S3WAKE_BIOS_PATH; - } -#endif pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 8e9a93a58c..1c2ab34ac5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -533,12 +533,9 @@ static me_bios_path intel_me_path(device_t dev) struct me_hfs hfs; struct me_gmes gmes; -#if CONFIG_HAVE_ACPI_RESUME /* S3 wake skips all MKHI messages */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) return ME_S3WAKE_BIOS_PATH; - } -#endif pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES); |