| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-07-16 | southbridge/intel: add IS_ENABLED() around Kconfig symbol references | Martin Roth |
| 2016-12-06 | intel PCI ops: Remove explicit PCI MMCONF access | Kyösti Mälkki |
| 2016-08-31 | src/southbridge: Code formating | Elyes HAOUAS |
| 2016-07-28 | bootmode: Get rid of CONFIG_BOOTMODE_STRAPS | Furquan Shaikh |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-22 | Revert "Remove sandybridge and ivybridge FSP code path" | Martin Roth |
| 2015-10-03 | Remove sandybridge and ivybridge FSP code path | Alexandru Gagniuc |
| 2015-06-04 | devicetree: Discriminate device ops scan_bus() | Kyösti Mälkki |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-02-15 | x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer | Kevin Paul Herbert |
| 2014-12-02 | Replace hlt with halt() | Patrick Georgi |
| 2014-06-21 | intel boards: Use acpi_is_wakeup_s3() | Kyösti Mälkki |
| 2013-12-04 | Add Intel FSP bd82x6x southbridge support | Marc Jones |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |