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2022-10-06sb/intel/common/gpio.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba746431496b30daba098716337b688314eac283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/pmbase.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/rtc.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/early_smbus.h: Add <device/pci_type.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-16bd82x6x/early_pch: enable smbus in bootblock stageHusni Faiz
SMBus is typically enabled in the ROMSTAGE. To get the BOOTBLOCK console message, the SMBus should be enabled in the BOOTBLOCK stage. Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-04arch/x86/acpi: Consolidate POST code handlingAngel Pons
Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-24southbridge/intel: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I28de2bade9a0deb163364856b9f2eabe3d3a7a11 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-03-08sb/intel/common/firmware: Hook up adding 10GbE LAN firmwareJeff Daly
Add ability to use ifdtool to add LAN firmware to image using Kconfig Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25sb/intel/common/hpet: use HPET_BASE_ADDRESS definitionFelix Held
Use the definition from arch/x86 instead of a local redefinition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-17sb/intel/common/firmware: Reword me_cleaner warningAngel Pons
That vendor firmware still works after applying `me_cleaner` doesn't mean that coreboot will also work with the same broken ME firmware. Instead, one should first test coreboot with the original, unmodified ME firmware to make sure coreboot works properly, and only then consider using `me_cleaner` with coreboot. Otherwise, one would end up with a non-booting or otherwise misbehaving system when trying to use coreboot and `me_cleaner` without having tested coreboot with the original ME firmware beforehand, which is hard to diagnose as the problem may only happen when the ME isn't running normally. Change-Id: I1626d747a99969faf7db37c10cf7d87e3977744a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-05src/southbridge: Remove unused <string.h>Elyes HAOUAS
Change-Id: Idc0cd9d6865cd9c1b95e6c838795cce9dbc643a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23sb/intel/common/rcba_pirq: Use correct size_t length modifierPaul Menzel
Building an image for the Lenovo T60 with `x86_64-linux-gnu-gcc-11` fails with the format warning below. CC ramstage/southbridge/intel/common/rcba_pirq.o src/southbridge/intel/common/rcba_pirq.c: In function 'intel_acpi_gen_def_acpi_pirq': src/southbridge/intel/common/rcba_pirq.c:86:69: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 86 | printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%ld\n", | ~~^ | | | long int | %d 87 | dev_path(dev), int_pin - PCI_INT_A, 88 | pirq_idx(pin_irq_map[map_count].pic_pirq)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} The return value of `pirq_idx()` is of type `size_t`, so use the appropriate length modifier `z`. Change-Id: I7af24cee536b81e4825b77942bcac75afeb9f476 Found-by: gcc (Debian 11.2.0-13) 11.2.0 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19southbridge/intel/common: Add an option to allow stitching of CSE binaryFurquan Shaikh
In the following changes, CSE binary for some platforms will be stitched at build time instead of adding a pre-built binary. This change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to select if it wants to stitch CSE binary instead of adding a pre-built one. In this case, ME_BIN_PATH is not visible to user and instead mainboard and/or SoC code is expected to provide the recipe for stitching the CSE image. BUG=b:189177580 Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14sb/intel/common: Hide IFD options if !HAVE_IFD_BINAngel Pons
When `HAVE_IFD_BIN` is not enabled, do not show IFD-related options. Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-29southbridge/intel/common: Move invalid PIRQ value to 0Tim Wawrzynczak
This makes structs that contain an `enum pirq` field that is default-initialized have the value PIRQ_INVALID Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21security/intel: Add option to enable SMM flash access onlyAngel Pons
On platforms where the boot media can be updated externally, e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps SMMSTORE working for use in payloads. Note that this breaks flashconsole, since the flash becomes read-only. Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection works as expected, and SMMSTORE can still be used. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common/pmclib: Use pmbase functionsArthur Heymans
Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Fix platform_is_resuming()Arthur Heymans
platform_is_resuming() was using the wrong register (PM1_STS) to figure out if the platform was resuming (PM1_CNT). Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Implement acpi_is_wakeup_s3()Arthur Heymans
acpi_is_wakeup_s3() requires acpi_get_sleep_type(). Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-05sb/intel/lynxpoint: Fix VBOOT with !CONFIG_INTEL_LYNXPOINT_LPArthur Heymans
The Intel Basking Ridge CRB does not have a Lynxpoint LP PCH but was using the lp gpio code instead of the southbridge/intel/common code in verstage. Change-Id: I775d3dc3540fbd8a939701d873183dd016e24ba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-27sb/intel/common: Refactor _PRT generation to support GSI-based tablesTim Wawrzynczak
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-21{sb,soc}/intel: Use `get_int_option` functionAngel Pons
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-19sb/intel/common: Drop some PCH_LPC_DEV macrosAngel Pons
The macro definitions depend on __SIMPLE_DEVICE__ and are only used in the get_gpio_base() or lpc_get_pmbase() functions, which already guard PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor. Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06sb/intel/*/smihandler.c: Correct BIOS_CNTL access widthAngel Pons
The BIOS_CNTL register is 8 bits wide on all affected platforms. Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24sb/intel/common: Use new acpigen_write_PRT_*_entry functionsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-07sb/intel/common/pciehp: Replace HP dummy device with common codeArthur Heymans
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports. Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works. Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph
2021-02-18southbridge: Ensure common Kconfig gets included lastAngel Pons
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-16sb/intel: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I19d01e1837b1ee946c66d4cc22a5138b64d72078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50577 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13sb,soc/intel: Add HPTS() for HPET visibilityKyösti Mälkki
Based on the detected OS the HPET ACPI device needs to be hidden sometimes. Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12sb/intel/common: Move named packages out of methodAngel Pons
IASL complains that creation of named objects within a method is highly inefficient. Avoid this by moving these named objects out of the method. Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-08soc/intel: Guard TRAP method in ASLKyösti Mälkki
Needed to support build with ACPI_SOC_NVS=n as SMIF object inside GNVS disappears then. Change-Id: Ib798187c24996b74d6345080f7d48c3f657eb512 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07sb/intel: Extract `set_global_reset` functionAngel Pons
To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-06intel: Define `RCBA_LENGTH` in Kconfig and use itAngel Pons
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01sb/intel/common/rcba.h: Guard RCBAx macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28southbridge/intel: Define default value for ME_REGION_ALLOW_CPU_READ_ACCESSSridhar Siricilla
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config. It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is integrated. TEST=Verified build for JSL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26sb,soc/intel: Refactor power_on_after_fail optionKyösti Mälkki
It's only necessary to call get_option() with SLP_TYP S5. Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki
Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25sb/intel/common: Change some SMI loggingKyösti Mälkki
Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25cpu/x86/smm: Use common APMC loggingKyösti Mälkki
Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15nb/intel/pineview: Extract HPET setup and delay functionAngel Pons
To allow other platforms to reuse this code, extract it into a separate compilation unit. Since HPET is enabled through the southbridge, place the code in the southbridge scope. Finally, select the newly-added Kconfig option from i82801gx and replace lpc.c `enable_hpet` function. Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08*/Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14sb/intel/common/smbus_ops.c: Clean up read resourcesAngel Pons
Using `pci_dev_read_resources` works just as well on bd82x6x (the allocator does the same) and allows dropping the i82801gx check. Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11sb/intel/x/smbus.c: Factor out common codeAngel Pons
Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07sb/intel/common: Modify CONFIG_LOCK_MANAGEMENT_ENGINE behaviorSridhar Siricilla
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents writing to ME region but keeps read access enabled. Since CSE Lite driver checks the signature of RW partition to identify the interrupted CSE firmware update, so host must have read access to the ME region. Also, the patch modifies the KConfig's help text to reflect the change. When CSE Lite SKU is integrated, master access permissions: FLMSTR1: 0x002007ff (Host CPU/BIOS) EC Region Write Access: disabled Platform Data Region Write Access: disabled GbE Region Write Access: disabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled EC Region Read Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: disabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled BUG=b:174118018 TEST=Built and verified the access permissions. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2020-11-04sb/intel/common/acpi/pcie.asl: Generalise file commentAngel Pons
This file is no longer specific to 6 and 7 series PCHs. Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/common/acpi/irqlinks.asl: Clean up cosmeticsAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I8562fc3278144380b0ab842d88176114821be823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21src/southbridge: Drop unneeded empty linesElyes HAOUAS
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26southbridge/intel/common: Replace outb with post_code in finalize.cSindhoor Tilak
The outb() call is replaced with the post_code() The post_codes.h is replaced with console.h since console.h includes both the post_code definition and post_codes.h Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7 Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-21ironlake/ibexpeak: Move early_smbus.c to common codeAngel Pons
We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-12sb/intel/common/acpi/irqlinks.asl: Add missing IRQsAngel Pons
IRQ 10 and IRQ 11 are valid for all southbridges using this code, as per their respective datasheets. So, add them for the sake of completeness. Change-Id: Ib4504861ed316a95b9735e0ed79f108f18071b3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43158 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08sb/intel: Factor out irqlinks.aslAngel Pons
Files are identical for all southbridges, except bd82x6x. We will take care of that in subsequent commits. Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08sb/intel: Factor out ICH ACPI for HDAAngel Pons
Files are identical between all three southbridges, and differ for PCH. Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06src/**/acpi/smbus.asl: Drop dead codeAngel Pons
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code isn't even being tested. So, throw it into the bitbucket before it rots any further. If anyone needs that code ever again, it's in git history. Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-27sb/intel/common: Add early SPI codeAngel Pons
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-16sb/intel/common/pmutil: Add dump_all_status()Kyösti Mälkki
Change-Id: I10582941afd68425603f6c4cadd228797cd098e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb/intel: Clean up some SMI enablesKyösti Mälkki
Change-Id: I191ad709fd3c6f906cd34b0053eeaebdb80d410d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14southbridge/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Modify southbridge/intel/common .asl files to comply with ASL2.0 syntax for better code readability and clarity BUG=none BRANCH=none TEST= Google Parrot platform coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia11769d5ac6154ed79d967d7bab36e12a1db751a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42084 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685 Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12southbridge/intel/common: Add Process CallChristian Walter
Add functionality to use process call cycle. It can be used to write/read data to/from e.g. EEPROM attached to SMBus Controller via I2C. Tested on: * C246 Change-Id: Ifdac6cf70a4ce744601f5d152a83d2125ea88360 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39875 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Revert "sb/intel/common/acpi: Add more Windows versions"Nico Huber
This reverts commit cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f. Advertising certain Windows versions triggers different paths in the OS. As there may also be device specific quirks in the OS, such changes need to be tested thoroughly on all affected devices. There was at least one very subtle regression introduced by this. When Linux sees "Windows 2012" support advertised, it disables the `acpi_video` backlight controls, at least on devices with Intel IGD. Without user-space handling the ACPI events, keyboard backlight controls stop working. Moreover, the commit message didn't state any reason for this change. Why was it merged? Change-Id: I722075f8e8f836b039fb8b8277e665fb49dac8f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08southbridge/*/Kconfig: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I339b455683ad481720b67a322bf51c891c2b611d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41142 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND registerElyes HAOUAS
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line lengthElyes HAOUAS
Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28security: Add common boot media write protectionPatrick Rudolph
Introduce boot media protection settings and use the existing boot_device_wp_region() function to apply settings on all platforms that supports it yet. Also remove the Intel southbridge code, which is now obsolete. Every platform locks the SPIBAR in a different stage. For align up with the common mrc cache driver and lock after it has been written to. Tested on Supermicro X11SSH-TF. The whole address space is write-protected. Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-04src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06sb/intel/common/firmware/Makefile.inc: use ifdtool --output flagMarcello Sylvester Bauer
Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-01sb/intel/common/acpi: Add more Windows versionsPeter Lemenkov
For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12sb/intel/common: Move SMBus register layout outside headerKyösti Mälkki
Change-Id: I841cc3bd636414c59af15d64d3f96b9be158af98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 01:50:58 +0000