| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-09-19 | sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode | Nathaniel Roach |
| 2017-09-13 | sb/intel/bd82x6x: Add time-stamp around ME DRAM update | Nathaniel Roach |
| 2016-12-06 | intel PCI ops: Remove explicit PCI MMCONF access | Kyösti Mälkki |
| 2016-07-31 | src/southbridge: Capitalize CPU, RAM and ROM | Elyes HAOUAS |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-10-03 | sandybridge ivybridge: Treat native init as first class citizen | Alexandru Gagniuc |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2014-12-02 | Replace hlt with halt() | Patrick Georgi |
| 2013-03-22 | x86: Unify arch/io.h and arch/romcc_io.h | Stefan Reinauer |
| 2012-04-04 | Add support for Intel Panther Point PCH | Stefan Reinauer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |