coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-09-21	src/southbridge: Drop unneeded empty lines	Elyes HAOUAS
2020-06-10	sb/intel/bd82x6x: Use PCI bitwise ops	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-04-29	sb/intel/bd82x6x: Use system_reset()	Elyes HAOUAS
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-12-19	southbridge: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2018-05-29	sb/intel/{bd82x6x,ibexpeak}: Fix out of bounds access in intel_me_status()	Nicola Corna
2017-09-19	sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode	Nathaniel Roach
2017-09-13	sb/intel/bd82x6x: Add time-stamp around ME DRAM update	Nathaniel Roach
2016-12-06	intel PCI ops: Remove explicit PCI MMCONF access	Kyösti Mälkki
2016-07-31	src/southbridge: Capitalize CPU, RAM and ROM	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-03	sandybridge ivybridge: Treat native init as first class citizen	Alexandru Gagniuc
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-12-02	Replace hlt with halt()	Patrick Georgi
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2012-04-04	Add support for Intel Panther Point PCH	Stefan Reinauer