coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-07-17	sb/amd/sr5650: Add fine-grained bounds checking	Jacob Garber
2019-06-21	sb/amd/sr5650: Use 32 bit integers when disabling ports	Jacob Garber
2019-03-06	sb/amd: Use simple PCI IO config access	Kyösti Mälkki
2019-03-03	device/pci_ops: Drop unused parameter	Kyösti Mälkki
2019-01-06	device: Use pcidev_on_root()	Kyösti Mälkki
2019-01-04	device: Replace ugly cases of dev_find_slot()	Kyösti Mälkki
2018-12-19	southbridge: Remove useless include <device/pci_ids.h>	Elyes HAOUAS
2018-10-23	src: Remove unneeded whitespace	Elyes HAOUAS
2018-06-14	src: Get rid of unneeded whitespace	Elyes HAOUAS
2018-05-23	sb/amd/sr5650: Get rid of device_t	Kyösti Mälkki
2015-12-08	sb/amd/sr5650: Allow resource allocator to assign bus numbers	Timothy Pearson
2015-11-23	southbridge/amd/sr5650: Hide clock configuration device after setup is complete	Timothy Pearson
2015-11-15	src/southbridge/amd/sr5650: Always configure lane director on startup	Timothy Pearson
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-24	southbridge/amd/sr5650: Fix hardcoded printk() function names in pcie.c	Timothy Pearson
2015-10-24	southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16	Timothy Pearson
2015-10-23	southbridge/amd/sr5650: Fix GPP3a link training in higher width modes	Timothy Pearson
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-12-17	southbridge/amd amd81XX, cs553X & sr5650 spelling fixes	Martin Roth
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-10-30	Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.	Stefan Reinauer
2011-07-22	Update AMD SR5650 and SB700	efdesign98
2011-03-27	Add AMD SR56x0 support.	Zheng Bao