coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2011-06-22	Rename {CPU\|NB\|SB}/amd/*_wrapper folders	efdesign98
2011-06-20	sb800: move spi prefetch and fast read mode to sb bootblock.	Stefan Reinauer
2011-06-19	ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic	Scott Duplichan
2011-06-09	Revert changes to set the sb800 to AHCI mode.	Marc Jones
2011-06-07	re-indent, so files conform to coding guidelines.	Stefan Reinauer
2011-06-01	trivial remove blanks at the end of line	Kerry She
2011-06-01	This patch fix a AMD sb800 wrapper compile warning:	Kerry She
2011-05-16	cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()	Peter Stuge
2011-05-15	Update gpp port configuration.	Scott Duplichan
2011-05-15	Program the I/O APIC ID.	Scott Duplichan
2011-05-15	Enable AHCI mode and hide IDE controller to reduce boot time.	Scott Duplichan
2011-05-15	Configure CIMx to use 33 MHz fast mode for SPD read.	Scott Duplichan
2011-05-07	SB800 CIMX code can share the AGESA V5 lib code,	Kerry She
2011-04-20	drop dead code from sb800 bootblock	Stefan Reinauer
2011-02-15	SERIAL_POST was renamed to CONSOLE_POST a while ago	Stefan Reinauer
2011-02-14	This code provides southbridge initialization for SB800 south bridges. It is...	Frank Vibrans
2011-01-18	remove the code which is not ready to release.	Zheng Bao
2011-01-11	change a readable way to fix SB800 CIMX "multi-character constant warning".	Kerry She
2011-01-01	src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.	Uwe Hermann
2011-01-01	AMD SB800: Drop component prefix from filenames.	Uwe Hermann
2011-01-01	Add AMD SB800 southbridge support via cimx_wrapper.	Kerry She