coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-06-11	AMD/CIMx: Add functions for AMD PCI IRQ routing	Mike Loptien
2014-05-13	southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge	Edward O'Callaghan
2014-04-20	AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS	Kyösti Mälkki
2014-02-06	usbdebug: Move under drivers/usb	Kyösti Mälkki
2013-07-01	usbdebug: Drop duplicates of EHCI BAR relocation code	Kyösti Mälkki
2013-04-18	AMD/SB800: Define the GPP PCIe lane distribution	Dave Frodin
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-02-23	AMD/Persimmon: Add RTC init to CIMX SB800	Mike Loptien
2012-12-12	SB800: Add IMC ROM and fan control.	Martin Roth
2012-11-27	Enable the FCH GPP port prior to device enumeration	Dave Frodin
2012-08-05	AMD SB: Call the rtc update if needed (Propagation)	zbao
2012-05-08	Clean up #ifs	Patrick Georgi
2012-04-12	Add Southbridge support for S3.	zbao
2011-10-12	SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode	Kerry Sheh
2011-10-12	sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE	Kerry Sheh
2011-10-11	mainboard: complete the sb800 devicetree even device is off	Kerry Sheh
2011-09-07	AMD F14 southbridge update	Kerry She
2011-06-29	amd southbirdge sb800 wrapper, pci bridge fix	Kerry She
2011-06-22	Rename {CPU\|NB\|SB}/amd/*_wrapper folders	efdesign98