coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-12-21	sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessor	Kyösti Mälkki
2019-12-20	AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK	Kyösti Mälkki
2019-12-04	sb/amd/cimx/sb800: add C bootblock southbridge initialization	Michał Żygowski
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2017-06-30	southbridge/amd: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-10-07	src/southbridge: Remove unnecessary whitespace	Elyes HAOUAS
2016-07-31	src/southbridge: Capitalize CPU, RAM and ROM	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-05	soutbridge/*/bootblock: Use pci_dev_t over device_t typedef	Edward O'Callaghan
2014-02-04	AMD cimx/sb800: Set SPI frequency and prefetch	Kyösti Mälkki
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-06	AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio	Jens Rottmann
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2011-11-01	remove trailing whitespace	Stefan Reinauer
2011-07-14	Move AMD SB800 early clock setup.	Scott Duplichan
2011-07-14	Set SB800 ROM decode size based on kconfig.	Marc Jones
2011-06-22	Rename {CPU\|NB\|SB}/amd/*_wrapper folders	efdesign98