coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2014-07-15	AGESA hudson: Fix SPI writes	Kyösti Mälkki
2014-07-14	AMD SPI: Optimise for longer writes	Kyösti Mälkki
2014-07-14	SPI: Split writes using spi_crop_chunk()	Kyösti Mälkki
2014-07-05	spi: Change spi_xfer to work in units of bytes instead of bits.	Gabe Black
2014-07-05	spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.	Gabe Black
2014-06-12	southbridge/amd: Change #if defined to #if IS_ENABLED	Dave Frodin
2014-04-20	southbridge/amd/agesa/hudson: Refactor SPI controller driver	Alexandru Gagniuc
2014-04-15	southbridge/amd/agesa/hudson: Clean up AGESA #includes	Alexandru Gagniuc
2013-08-05	AMD Kabini: Modify Hudson southbridge to support new AMD processor	Siyuan Wang
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-02-11	spi.h: Rename the spi.h to spi-generic.h	Zheng Bao
2012-12-12	Claim the SPI bus before writes if the IMC ROM is present	Martin Roth
2012-11-30	AMD S3: Leverage the public SPI routine	Zheng Bao
2012-07-14	AGESA F15 wrapper for Hudson.	zbao