coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-11-23	AGESA binaryPI: Fix PCI ID namespace	Kyösti Mälkki
2016-07-31	src/southbridge: Capitalize CPU, RAM and ROM	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-06-08	southbridge/amd/{agesa,pi}/hudson/lpc.c: Sync together	Edward O'Callaghan
2015-06-04	devicetree: Discriminate device ops scan_bus()	Kyösti Mälkki
2015-05-26	acpi: Remove monolithic ACPI	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-12-30	drivers/pc80/mc146818rtc: Assume we always have ALTCENTURY	Gabe Black
2014-12-17	southbridge/amd agesa & cimx spelling fixes	Martin Roth
2014-11-26	agesa/family15tn: Switch to per-device ACPI	Vladimir Serbinenko
2014-10-22	cmos: Rename the CMOS related functions.	Gabe Black
2014-07-30	model_fxx/processor_name.c, hudson/lpc.c: add missing break statements	Daniele Forsi
2014-06-11	amd/southbridge/lpc: SPI BAR has fixed size/location	Dave Frodin
2014-06-11	amd/hudson: Add the IOAPIC space to the fixed resources table	Dave Frodin
2014-04-06	amd/agesa/hudson: Implement PNP resource setup in LPC bridge	Rudolf Marek
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2013-02-25	AMD Southbridge: Add RTC init to lpc_init	Mike Loptien
2012-12-12	Fix SPI BAR special case in lpc_set_resources	Martin Roth
2012-11-28	Remove assembly coded log2 function	Ronald G. Minnich
2012-08-02	AMD hudson: Call the rtc update if needed.	zbao
2012-07-14	AGESA F15 wrapper for Hudson.	zbao