coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-08-17	Fix PCI ACPI _OSC methods	Marc Jones
2017-11-28	AMD platforms: Fix ASL comment that implies "\_SB" is southbridge	Martin Roth
2017-08-23	AGESA binaryPI: Consolidate and fix sleep states	Kyösti Mälkki
2017-06-30	southbridge/amd: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-12-05	mainboard & southbridge: Clear files that are just headers	Martin Roth
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2015-12-10	ACPI: Fix IASL Warning about unused method for _OSI check	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-07-12	Verify Kconfigs symbols are not zero for hex and int type symbols	Martin Roth
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-20	AGESA: Remove redundant Avalon support from Hudson	Kyösti Mälkki
2014-10-23	AMD Hudson: enable IMC fan control using ACPI code	WANG Siyuan
2014-08-30	AMD Steppe Eagle: New integrated southbridge (Avalon)	Bruce Griffith
2014-06-14	amd/agesa,cimx: Rename ACPI OS detection methods	Edward O'Callaghan
2014-04-21	AMD hudson and yangtze boards: Let mainboard declare power button	Alexandru Gagniuc
2014-04-13	hudson boards: Don't require ide.asl file on boards without IDE	Alexandru Gagniuc
2013-12-07	Correct file permissions.	Idwer Vollering
2013-08-15	AMD Fam16: Add OSC method to PCI0	Mike Loptien
2013-08-15	AMD Fam16: Add secondary bus number to CRES method	Mike Loptien
2013-08-15	AMD Kabini: Split DSDT into common sections	Mike Loptien
2013-08-08	ASUS F2A85-M: Split DSDT into common sections (as per Parmer)	Kimarie Hoot
2013-07-16	AMD Fam15tn: Split DSDT into common sections	Steve Goodrich