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Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The patch add APIs to check CSE Region's write protection information.
Also, adds helper functions to get the SPI controller's MMIO address
to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read
protection details.
During the coreboot image build, write protection is enabled for CSE RO.
It is enabled through a Intel MFIT XML configuration.
TEST=Verify write protection information of CSE Region
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This will allow configuring the concerned config through an external
defconfig file.
BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch adds TCSS XHCI device ID for ADL-N CPU which is required
for USB3 port enumeration.
Document Reference: 645548 revision 1.0 (Chapter 2.3)
BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are
generated for device 0d.0
Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Originally, dram size is hard-coded to 4GB by default. To support
different dram size, calculate it from the mem chip info stored
in CBMEM.
BUG=b:206014043
TEST=Output "dram size: 0x100000000" on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Store dram info in cbmem for ramstage or payloads to use.
BUG=b:206014043
TEST=Build pass on Kingler
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change provides config for devicetree to control ASPM per port
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles on taeko.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch creates a new helper function to enable P2SB BAR.
`p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F)
and BAR address (combining high and low base addresses).
BUG=b:224325352
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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In MT8186, we need to disable spm_thermal to prevent it from
influencing other wdt status.
There are two hardware pathes which are used for asserting watchdog
from thermal. We can disable status of path 1 because status of
path 2 is used.
1. Thermal -> SPM -> WDT
2. Thermal -> WDT
Spm_thermal (path 1) is a flexible option for software control, and
the hardware designer suggests that we should disable it if we don't
use it.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Because we close external signal in kernel driver since MT8195, it's
more reasonable to trigger sw reset with exteranl signal again
whenever the wdt status is not equal to 0.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without setting the set_resources field for soc_ops, we will get an
error during device initialization:
[ERROR] CPU_CLUSTER: 0 missing set_resources
Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.
BUG=b:224419346
TEST=emerge-corsola coreboot
TEST=Did not see the error on krabby
BRANCH=none
Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This message is not really an error message, so BIOS_ERR is
inappropriate. The message does seem more like a warning though,
that the developer could have multiple Kconfigs selected to send EOP,
therefore switch to BIOS_WARN instead.
BRANCH=firmware-brya-14505.B
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I57a34334007a6a7443302c2f25de3d5c87c85573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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TCSS ASL code was carried forward from TGL and it used to follow the same
sequence.
Recently as part of s0ix hang issue, it was found that sending IOM
MCTP command as part of TCSS D3 Cold enter-exit sequence created an
issue.
We discovered that due to change in hardware sequence, ADL should not
set/reset IOM MCTP during D3 cold entry or exit. This patch removes the
bit setting from ASL file to prevent hang in the system.
This patch also removes obsolete Pcode mailbox communication which is
no longer required for ADL.
BUG=b:220796339
BRANCH=firmware-brya-14505.B
TEST=Check if hang issue is resolved with the CL and no other regression
observed
Change-Id: I2f066bcc4a8f475a15ddd12ef5ed87d7298312bb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62861
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to
BIOS_INFO instead.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I9dc852a0cd30f95506c205f161a05e8a8c44fcd5
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch refactors the current P2SB common code driver to accommodate
the future SoC platform with provision of more than one P2SB IP in
disaggregated die architecture.
IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with
MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is
renamed as SoC in MTL.)
P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c
is added only for PCH/SoC P2SB.
BUG=b:224325352
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This change supports the configuration and enablement of
mdp clock to vote for turbo and supports different display
panel resolutions and framerates.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ADL-P MCH ID 4, 8, 9, 10 into this list.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Cache the BIOS region and extended BIOS region if the boot device is
memory mapped, which is mostly the case with Intel SoC platform.
Having the ROM region cached helped to improve the pre-boot time.
TEST=Able to boot redrix to Chrome OS without seeing any sluggishness.
Additionally verified on EHL board (from siemens), shows significant
savings in payload loading time as below:
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch provides a way to cache `ext_bios` region for all stages to
save boot time.
TEST=Able to see the ext_bios region in MTRR snapshot when cached on
the Brya variants.
Here is the timestamp snippet showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87139a9ed7eb9ed43164a5199aa436dd1219145c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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As per ME BWG, the patch retries MEI CSE DISABLE command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.
TEST=build and boot the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.
BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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Add chip config for setting PCIe config.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.
BUG=b:222694093
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US,
which controls how long to wait for an I2C devices to
produce/accept all the data bytes in a single transfer.
(The device can delay transfer by stretching the clock of
the ack bit.)
The default value of this new setting is 500ms. Existing
code had timeouts anywhere from tens of milliseconds to a
full second beween various drivers. Drivers can still have
their own shorter timeouts for setup/communication with the
I2C host controller (as opposed to transactions with I2C
devices on the bus.)
In general, the timeout is not meant to be reached except in
situations where there is already serious problem with the
boot, and serves to make sure that some useful diagnostic
output is produced on the console.
Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add PCI ID's for APL/GLK so they can use HDA.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
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The pmic hwcid dumping should not be a warning, so we modify it to info.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a930b69bd45d5f0d84c3d269ca721b287dbadea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.
BUG=b:222217317
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.
This patch hooks up this parameter to devicetree
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Check code compiles and correct value has been passed to FSP.
Change-Id: I2d7839d8fecd7b5403f52f3926d1d0bc06728ed9
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.
This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
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This patch adds `FSPM_UPD *` as argument for
mem_populate_channel_data() and read_spd_dimm().
This change will help to update the architectural FSP-M UPDs in
read_spd_dimm().
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I770cfd05194c33e11f98f95c5b93157b0ead70c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
|
|
The patch uses generic enum type values for EOP command handler. So,
it renames cse_eop_result enum type to cse_cmd_result and also renames
the enum values to have generic name.
TEST=Build the code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.
TEST=Verify HECI Interface reset in the simulated error scenarios.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The patch implements below changes:
1. Implements different error codes and use them in appropriate
failure scenarios of below functions:
a. heci_send()
b. recv_one_message()
c. heci_receive()
2. As heci_send_receive() is updated to return appropriate error codes
in different error scenarios of sending and receiving the HECI
commands. As the function is updated to return 0 when success, and
non-zero values in the failure scenarios, so all caller function have
been updated.
BUG=b:220652101
TEST=Verified CSE RX and TX APIs return error codes appropriately in
the simulated error scenarios.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table after normalizing to the zero-point value. Although
consumer CSE sku also supports this feature, it was validated on
CSE Lite sku only.
BUG=b:182575295
TEST=Able to see TS elapse prior to IA reset on Brya/Redrix
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 88,000
945:CSE started to handle ICC configuration 88,000 (0)
946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000)
947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000)
0:1st timestamp 330,857 (48,857)
11:start of bootblock 341,811 (10,953)
12:end of bootblock 349,299 (7,487)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.
replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.
I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.
BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Enable PCIe support for mt8195.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early
stage to reduce the impact of 100ms delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6799c53b03a33be91157ea088d829beb4272976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Log the platform boot mode reported by PSP verstage to PSP stage 1
bootloader. This helps to improve the debuggability.
BUG=b:193050286
TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot
mode is logged in the verstage logs.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I752ee56f2af48215a770d799432d02f0609757cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
|
|
As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.
Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.
Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.
Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.
BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.
Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
Earlier while trying to optimize boot time End Of Post (EOP) time kept
increasing (~80 ms) when boot time decreased to around 1 second.
This was because CSE was busy with own firmware loading.
When EOP was moved later in boot stage it again created issue since CSE
got busy with other payload loading for OS boot, so response to EOP
got delayed by ~70-80 ms.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow
where FSP used to send EOP once silicon init is done and coreboot used
to rely on FSP to send this message.
Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP
time reduces from ~60 ms to ~20 ms on Brya QS board.
Since this setting might vary for each SoC, SoCs can decide when to send
EOP in the boot sequence. This patch adds Kconfig option to send EOP via
SoC
BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Code compilation is fine for Brya board. Boot time test is done
using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms.
Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Hook up vtd_enable to CMOS value of "vtd".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16b43f0489f652d650e820c36b2b9bea61cf3c8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This solved the error:
i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
i801_smbus 0000:00:1f.1: PCI INT A: not connected
i801_smbus 0000:00:1f.1: SPD Write Disable is set
i801_smbus 0000:00:1f.1: SMBus using polling
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reference: chapter2 in Meteor Lake EDS vol1 (640228)
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
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Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.
On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.
FMAP REGION: ME_RW_A
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
FMAP REGION: ME_RW_B
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook PCH_DEVFN_CNVI (0c.0) to CnviMode.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8b51e98952a39bd432e9bc63eea57a40dd6cf106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add PCIe support for MediaTek platform.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
- linux/drivers/pci/controller/pcie-mediatek-gen3.c
This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Device 1f.7 is TraceHub, not the PCH Thermal device, which doesn't exist
anymore on TGL. Correct the device´s alias.
Reference: Intel doc# 631119-007
Change-Id: I30a4ab1e801f6cdb0f2e03f105bf8cc09592eed8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I937bdf032e1ed86900334d41655f3e6272f66a6f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Denverton is a special version of IFD2 flash layout. It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have. Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.
TEST='ifdtool -p dnv coreboot.rom' and verify correct output
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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These helpers are not architecture dependent and it might be used for
different platform.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Windows complains on missing drivers for these ACPI devices. Hide them
from OS as it doesn't influence the hardware operation. Linux can
still probe the drivers correctly.
TEST=Boot Windows 11 and see there are no devices with missing drivers.
Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are
still probed.
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch uses Kconfigs for Descriptor Region and Descriptor Region
size instead of locally defined macros
TEST=Build and boot Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f9461c8604383f995a4438f45286b14fb94deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
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The patch defines Kconfigs for FMAP Descriptor Region and Descriptor
Region size. The Kconfigs will be used by follow-up patches.
TEST=Build Brya code
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia3481acefbda885617607675aef2afbb81c21c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Move some structures to common folder (CB:61293), so we need to update
header version.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Id82cbef9cb10dba71489ea96f67c329de9aadc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Move some structures to common folder (CB:61293), so we need to update
header version for this.
BUG=none
TEST=dram calibration pass
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I8cf12f4967af116eaef88c1f688567f1da9fa6e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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In the northbridge's and root complex' read_resources function, the
mmconf resource used the number of the MMIO_CONF_BASE MSR as index which
might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Since we want to read the non-x86 CBMEMC from SMM we need to be stricter
on where we read from. This change forces the verstage binary and x86
code to agree on the CBMEMC transfer buffer location and size.
BUG=b:221231786
TEST=Boot guybrush and verify verstage transfer buffer still ends up in
cbmem
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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We don't need to force the caller to look up and cast the transfer
region. We can do it in the function.
BUG=b:221231786
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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I want to reuse the transfer buffer methods in SMM, so I need to add
them into their own file. I renamed `setup_cbmem_console` to
`replay_transfer_buffer_cbmemc` so it has a more descriptive name. I
also fixed the comment on `verify_psp_transfer_buf`.
BUG=b:221231786
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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We need to save the transfer buffer so we can transfer the cbmem
console and timestamps into x86 DRAM.
BUG=b:221231786
TEST=Boot guybrush and verify S0i3 resume works. Also dumped the
transfer buffer from the OS and verified the console contents got
transferred.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.
This implementation is according to chapter 5.13 in MT8186 Functional
Specification.
BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.
Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot should skip sending EOP during S3 resume since CSE doesn't
require EOP in resume path.
Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage
which doesn't get called during S3 resume.
In case EOP is moved in earlier stage, coreboot might send EOP in S3
resume as well. This patch adds check before calling cse_send_eop.
BUG=b:211085685
BRANCH=None
TEST=Check by moving EOP to earlier stage. EOP sending is skipped during
S3 resume.
Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD. However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.
ACPI Error: AE_NOT_FOUND, While resolving a named reference package
element - \NULL (20200925/dspkginit-438)
Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.
Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
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