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This commit streamlines code and strengthens common code robustness
by moving the following SoC-layer functions to the common layer:
- sa_get_mmcfg_size: Retrieves the MMIO (Memory-Mapped I/O)
configuration space size by reading offset
0x60 of the PCI Host Bridge (D0:F0).
- sa_get_dsm_size: Calculates the size of the DSM (Device Stolen
Memory) by reading offset 0x50 of the PCI
Host Bridge (D0:F0) to determine pre-allocated
memory for the IGD (Integrated Graphics Device).
- sa_get_gsm_size: Calculates the size of the GSM (Graphics Stolen
Memory) by reading offset 0x52 of the PCI Host
Bridge (D0:F0).
- sa_get_dpr_size: Determines the size of the DMA Protection
Range (DPR) by reading offset 0x5C of the PCI
Host Bridge (D0:F0).
TEST= Build and boot successful on google/screebo.
Change-Id: Ic00e001563ec6f0d737a445964c716b45db43327
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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In follow up to CB:80285 use gpp_clk_setup_common for picasso as well.
Change-Id: I68d498d08d5975037086c84ff2f7fdb265ee84d9
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80414
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings picasso in line with cezanne, mendocino
and phoenix. This also prepares picasso to use the common function
gpp_clk_setup_common.
Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80413
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Leverages common SA header definitions for Host Bridge registers.
Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
Additionally, made some minor code alignment corrections while
adding newer macros in the header file.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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gpp_clk_setup code in most AMD SoC is similar and it can moved to common
code. The only thing which is SoC dependent in this function is the SoC
config, hence keep it in SoC code and move everything else in new
gpp_clk_setup_common function which is in soc/amd/common. Picasso and
Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so
they are addressed in later patches.
Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80285
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of S:B:D:F numbers pass the struct device to
acpi_create_srat_gia_pci and let it extract the information needed.
This also adds support for PCI multi segment groups.
Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80258
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of a BDF number store a pointer to the device itself.
Change-Id: I3fef93c5e54c8af792102bcd25364c43b554a5f0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84a7b7b1b2c45b773c6f10b39e7813db3f96546e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80408
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In commit 30f36c35e75a ("soc/amd: rework DRAM and fixed resource
reporting") the reporting of the DRAM resources was moved from the
northbridge PCI device to the domain device. amd_pci_domain_fill_ssdt
didn't skip those DRAM resources when generation the resource producer
ranges which made Windows 10 very unhappy when it tried to evaluating
the ACPI tables causing it to reboot in a loop. To fix this, add a check
to also skip the resources that have the IORESOURCE_STORED flag set when
generating the resource producer ranges for the PCI root.
TEST=Windows 10 now successfully boots and reboots again on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b6d3fd8c7f89aa4364de7963d745aef8d6b6f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80407
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It seems that we have some applications where we need to calculate a GCD
in 64 bits. Now, we could instantiate the algorithm multiple times for
different bit width combinations to be able to use the most efficient
one for each problem... but considering that the function usually only
gets called once per callsite per stage, and that software emulation of
64-bit division on 32-bit systems doesn't take *that* long either, we
would probably usually be paying more time loading the second instance
of the function than we save with faster divisions. So let's just make
things easy and always do it in 64-bit and then nobody has to spend time
thinking on which version to call.
Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80319
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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This makes it easier to reuse, e.g. if you want to do it twice in one
assembly file.
Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=b:248612503
TEST=Test with crrev.com/c/4756330
BRANCH=none
Signed-off-by: Yi Chou <yich@google.com>
Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80315
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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In case where PAD_CFG_GPI_INT() is initialized with a pin value
lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community
the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin.
Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by
find_free_unique_irq() during IRQ assignment and assigned to other pins
which causes IRQ conflicts
BUG=b:322984217
BRANCH=None
TEST=Boot test on brox, check if correct IRQ assigned to EC
Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Printing the data fabric MMIO decode window configuration might be
useful and it also aligns this SoC more with the other AMD family 17h+
SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52f6655a5c63e31165549dcb6f5f95d4e74bad3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Drop the unneeded data_fabric_set_mmio_np function and the corresponding
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION Kconfig symbol. In systems
with only one FCH, its MMIO region will be subtractively decoded and
there's no need to add a non-posted data fabric MMIO region after the
FSP/openSIL has already configured the data fabric decode windows. In
systems with more than one FCH, openSIL will already take care of
initializing everything for the additional FCH, so we also won't need to
do anything in that case. Since dropping this function also removes both
data_fabric_print_mmio_conf calls before and after adding the unneeded
non-posted MMIO region, replace the data_fabric_set_mmio_np call with a
data_fabric_print_mmio_conf call to still print the data fabric MMIO
decode regions set up by the FSP/openSIL.
TEST=Mandolin still boots successfully
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I474b6e066060abb3fe5b78505521c7782cc192ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Remove hardcoded B:D:F numbers for the first socket and pass the PCI
addresses to be locked within SMM by using the smm_pci_resource_store.
This allows to lock down SMM on all sockets without knowing the actual
bus topology or PCI segment group at compile time where the UBOX devices
reside on.
Tested: SMM is locked on all 4 sockets instead of just one.
Change-Id: Ica694911384005681662d3d7bed354a60bf08911
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80247
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, SOC_INTEL_COMMON_BLOCK_TCSS will set MUX to disabled. The two
related options to re-configure it for either USB devices or displays,
are currently only supported by the ChromeEC. As such, any device
without the ChromeEC will boot with attached USB-C devices in a
non-functional state.
Add TCSS_HAS_USBC_OPS to make this feature configurable, and set the
default to enabled if the board features the ChromeEC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia848668ae9af4637fc7cffec9eb694f29d7deba9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79882
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec96
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80301
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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This patch moves the IP checksum algorithm into commonlib to prepare for
it being shared with libpayload. The current implementation is ancient
and pretty hard to read (and does some unnecessary questionable things
like the type-punning stuff which leads to suboptimal code generation),
so this reimplements it from scratch (that also helps with the
licensing).
This algorithm is prepared to take in a pre-calculated "wide" checksum
in a machine-register-sized data type which is then narrowed down to 16
bits (see RFC 1071 for why that's valid). This isn't used yet (and the
code will get optimized out), but will be used later in this patch
series for architecture-specific optimization.
Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.
Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the USB configuration data structure is FSP-specific, add guards
on this part of the soc_amd_phoenix_config struct and the corresponding
include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6c324421fbc3dc7b9a7bf6f5868785e9718147a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80298
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since openSIL configures the APCI IO port addresses, coreboot should not
overwrite them.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If10e5a9f52ab313ad1afebd7f9e722994d48b0a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80297
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the calls to the openSIL stubs to do the silicon initialization, to
get the APCI IO ports, and to get the memory map.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80296
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The configuration of the PCIe clock generators in the FCH was moved from
the FSP to coreboot, since all registers are documented. This
initialization is however tightly integrated in the rest of the PCIe
init code inside the reference code. In the FSP case, this code was
manually removed. openSIL will do that part of the initialization so
that there's no coreboot-specific change needed in openSIL. This will
also avoid the problems caused by mismatching configurations done by the
coreboot code and the PCIe init part of the reference code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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In the FSP case we get this info via a HOB. It's currently unclear if
we'll get a data structure for this from openSIL or if we'll end up
being able to just read the configuration fro the hardware, so add a
get_pci_routing_table stub for now to be able to build.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5003e287d6a3a9320922beaffff8a3a846531e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Add the SOC_AMD_PHOENIX_OPENSIL Kconfig option to be able to build the
Phoenix code using openSIL instead of FSP for initializing the hardware.
Since there's currently no publicly available openSIL code for Phoenix,
SOC_AMD_OPENSIL_STUB is selected to have the stubs added to the build
instead of the actual openSIL code. The code added by selecting
SOC_AMD_COMMON_BLOCK_ACPI_CPPC relies on getting the information it
needs via a HOB, so for only select that option in the FSP case for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If597ff3dc824ce832399d3efde32352b36354b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove the unused soc/platform_descriptors.h include and add the missing
types.h include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0b066aa5dc657f7709f9cce734a025180bf5bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Only add the vendorcode/amd/fsp/phoenix and vendorcode/amd/fsp/common
folders to the include search path when the SOC_AMD_PHOENIX_FSP Kconfig
option is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18668ab8578b297c328fdc647c8a95f540ac6272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80288
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide 3 separate functions for each openSIL time point instead of one,
so that we don't need the xSIM-api header file to be included in
opensil.h to decouple the coreboot code more form the openSIL code. This
will allow to create an openSIL stub implementation to already get most
of the coreboot-side SoC code in place before the openSIL source code is
done and released.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Now that the SoC-specific memory map is reported on the domain device
instead of the northbridge device, factor out the
read_soc_memmap_resources function from root_complex.c to new memmap.c
file. For now each SoC still has its own memmap.c file, but the plan is
to eventually have a common implementation that works for all AMD family
17h+ SoCs. For that I'll still need to look closer into the differences
between the FSP and the openSIL integration though.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Only call read_fsp_resources if PLATFORM_USES_FSP2_0 is selected in
Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic63e0904ad04dbecfac1be4d59abbb8d4f9f11d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the
legacy PCI config space access is needed on all AMD SoCs, implement a
common add_pci_cfg_resources function that reports both and gets called
from amd_pci_domain_read_resources and don't report those in the SoC-
specific code any more. The only functional change is that on Genoa now
the IO ports used for the legacy PCI config space access get reserved.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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To make add_opensil_memmap match the other function that are directly or
indirectly called by amd_pci_domain_read_resources, pass the resource
index as a pointer instead of passing it by value and then returning the
new resource index.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Introduce read_soc_memmap_resources which gets called by
amd_pci_domain_read_resources for the first domain of the SoC to report
the DRAM and PCI config space access resources to the allocator. For
Genoa this allows to use amd_pci_domain_read_resources as read_resources
in the genoa_pci_domain_ops instead of needing to wrap that call to be
able to call add_opensil_memmap for the first domain. For the other
family 17h+ SoCs the moves the reporting of the DRAM resources and the
PCI config space access resources from the northbridge device to the
domain device.
TEST=Resources still get reported on Mandolin, but now under the domain
instead of the northbridge PCI device
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib19fd94e06fa3a1d95ade7fafe22db013045a942
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80268
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use an unsigned long as resource index type instead of an int to match
the data type used for the index in the resource struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f58e32a535326116460545287cc59aaf94166a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Use an unsigned long as resource index type instead of an int to match
the data type used for the index in the resource struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60ac0e30627001698565b7256421780f9a94bf65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80266
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Previously the code checked if the first downstream bus of the domain
was bus 0 in segment group 0 to only run certain code for the first
domain. Instead check if the domain number is 0 which should make the
code a bit easier to understand.
TEST=add_opensil_memmap still gets called exactly once on Onyx
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Instead of manually crafting S:B:D:F numbers for every
VTD device loop over the entire devicetree by PCI DEV IDs.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80092
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Attach UBOX stacks on newer generation Xeon-SP.
In order to use PCI drivers for UBOX devices, locating UBOX devices
by vendor and device IDs and replacing device access by specifying
S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the
PCI enumerator index all devices.
Since there are no PCI BARs on the UBOX bus the PCI locator doesn't
have to assign resources on those buses.
Once all PCI devices on the UBOX stack can be located without knowing
their UBOX bus number and PCI segment the Xeon-SP code can fully
enable the multi PCI segment group support.
Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID.
Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80091
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The x86 core always starts with an IP at 0xfff0. This needs to match in
the code.
Change-Id: Ibced50e4348a2b46511328f9b3f3afa836feb9a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Only call amd_fsp_silicon_init if PLATFORM_USES_FSP2_0 is selected in
Kconfig. I'm not 100% sure about the data_fabric_set_mmio_np call yet,
but since it doesn't depend on PLATFORM_USES_FSP2_0 to compile, I'll
look into that one later.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Move the definition of the TCO registers used in most boards to a
separate file and use it consistently. Do not unify TCO for older
incompatible platforms.
BUG=b:314260167
TEST=none
Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Multiple links are unused throughout the tree and make the code more
confusing as an iteration over all busses is needed to get downstream
devices. This also not done consistently e.g. the allocator does not
care about multiple links on busses. A better way of dealing multiple
links below a device is to feature dummy devices with each their
respective bus.
This drops the sconfig capability to declare the same device multiple
times which was previously used to declare multiple links.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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CXL IIO stacks
When an IIO stack is connected with CXL cards, its bus range
will be divided by a PCI host bridge object and a CXL host
bridge object, otherwise, all its range will be owned by the
PCI host bridge object. Accordingly, CXL ACPI resources should
be only created when the IIO stack is connected with a CXL
card.
TEST=intel/archercity CRB
Change-Id: I6c1b1343991bc73d90a433d959f6618bbf59532f
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80087
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently resource allocation starts top down from the default value
0xfe000000. This does not match what ACPI reports, so adapt
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that.
Change-Id: I32d08ffd5bbd856b17f7ca2775c5923957d92c85
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Adding downstream busses at runtime is a common pattern so add a helper
function.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The CRAT (Component Resource Attribute Table) isn't used on the APUs
from Renoir on and has also been marked as deprecated in version 6.5 of
the ACPI specification. So remove the 'TODO: look into adding CRAT'
comment from all SoCs from Renoir/Cezanne on.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3ea1e3678608b0ace2a1ff7fc104594e90c91476
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80227
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the acpi_add_fsp_tables implementation is identical for all SoCs,
factor it out and move it to the common AMD FSP code. Also guard the
acpi_add_fsp_tables call in soc_acpi_write_tables with
if (CONFIG(PLATFORM_USES_FSP2_0)) to properly handle the FSP dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8917a346f586e77b3b3278c73aed8cf61f3c9e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80225
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Factor out acpi_add_fsp_tables from the soc_acpi_write_tables function
and move the remaining parts of the soc_acpi_write_tables function to
the SoC's acpi.c. This aligns the other family 17h/19h SoCs more with
Genoa and only leaves the FSP-specific code in agesa_acpi.c which will
be made common in a following patch. I decided against also renaming
agesa_acpi.c to acpi_fsp.c, since that would have made the diff less
readable and the files get deleted in a following patch anyway.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia87ac0e77c5e673e694703b85a4bab85a34b980e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Factor out the code to add the CRAT ACPI table into a separate file and
add the acpi_add_crat_table function that can then be called from
soc_acpi_write_tables to better isolate all code specific to the CRAT
table.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a7853748512811d3d4e124224fcd459e527522c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80223
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to
the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are
now empty, delete those files too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the definition is the same for all SoCs, move it to the common
amdblock/acpi.h header. Since the Stoneyridge northbridge.c file also
includes this prototype, remove the static attribute of the function
there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9aa215f2b4ba58f43fed2c751d989f1719e0a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80221
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The southbridge_write_acpi_tables function uses a struct device type
parameter, but device/device.h that provides the definition wasn't
included.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5245fa132ec9b84bbc483a31788bcd6fac0736e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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add_agesa_fsp_acpi_table should use the same type for the 'current'
parameter and return value as the calling soc_acpi_write_tables does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie9f770b1d847ea28e4dbd96298a723d794b91a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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A pointer to soc_acpi_write_tables gets assigned to the
write_acpi_tables element of the device_operations struct, so make sure
that the function has the expected function signature which in this case
means using unsigned long as type for both the 'current' parameter and
the return value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iee45badb904fa20c6db146edbc00c40ca09361d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80218
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's not the AGESA code that generates most of the ACPI tables, so
rename the function. This also aligns the other SoCs more with Genoa.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b2e6c4cb7139c8bde01b4440ab2e923a1086827
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80217
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Added Lunar Lake device IDs the device specific functions
Reference:
Lunar Lake External Design Specification Volume 1 (734362)
Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Move the verstage on PSP files in vendorcode from the fsp subdirectory
to a new psp_verstage subdirectory, since those files aren't specific to
the case of the FSP being used for the silicon initialization.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Instead of open-coding this functionality in all AMD SoCs, factor it out
into a common implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idb65c398b747e70ec67107e0a1d4bd6551501347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80208
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Now that we've added an ACPI device for SATA, add the name back
to the soc_acpi_name() list so the PEPD LPI constraint list
generates a valid reference to the SATA device.
TEST=build/boot Win11 on google/puff (kaisa).
Change-Id: I134058f5ef78f419dc5538452614125ad44bf29d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80059
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add an ACPI stub containing the SATA device in proper scope, along with
the device status, so that there exists a device to be referenced from
the PEPD LPI constraint list. Fixes a Windows BSOD INTERNAL_POWER_ERROR
on devices with enabled SATA ports.
TEST=build/boot Win11 on google/puff (kaisa).
Change-Id: I951c62d09609ed73079fe97ea9ce49fdee333272
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
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This reverts commit d64b66ba267a217d0b6716309019c36c8cfdf8c2:
"soc/intel/cannonlake: Add missing min sleep state for thermal device."
Reverting because commit e00523aae2ea ("soc/intel/cannonlake: Drop
entries from soc_acpi_name()") removed the ACPI device name for the PCH
thermal device, since there is no ACPI device defined for it. Removing
the name without removing the minimum sleep state caused an invalid LPI
entry to be created, which caused a Windows BSOD: INTERNAL_POWER_ERROR.
TEST=build/boot Win11 on google/puff (wyvern).
Change-Id: I2dfe76d5f72cde7742cee338fa24eaafb84c4604
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80057
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Call setup_opensil, opensil_entry, and fch_init in the right order from
the init method of the SoC's chip operations. This brings this SoC both
more in line with the other SoCs and avoids using boot state hooks for
this which also makes the sequence in which those functions are called
easier to understand. Previously the boot states were used so that
setup_opensil was run before configure_mpio which was run before
opensil_entry(SIL_TP1), but since configure_mpio is called from
setup_opensil, this is no longer necessary.
TEST=Onyx still boots to the payload and the MPIO configuration reported
from the openSIL code is still the same. The FCH init code now runs
before the resource allocation like on the AMD SoCs that rely on FSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79985
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ida6e87908ae6996529057c8df12dbe046ee54b98
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie449267fe4fdd75110f577e1b9f748cd06140950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use a union to access the PCI domain ID.
This will become handy in the following commits to gather meta-data
from the domain ID.
Change-Id: I5c371961768410167a571358f6f366847a259eb6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80099
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The C_STATE_LATENCY_FROM_LAT_REG() macro uses values that we also
write into the respective MSRs in configure_c_states(). Match the
indices to those used there.
Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The code can now deal with stacks that have no resources so just hook
them all up.
Intel XEON-SP FSP reports all report the state of its stacks, which
comprise of PCI root bridges and their respective resources, like PCI
busses, IO and MEM resources, via HOB. Parsing all of those into native
coreboot structures makes it possible to handle those in a more native
fashion like use PCI drivers, native helper functions, ... As opposed
parsing those structures again out of the HOB each time. This makes code
reuse across the tree more feasible.
An additional advantage is that Linux does not need to redo resource
allocation since the one done by coreboot will be valid, which
potentially decreases boot time.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Connect the PCI domain to the bus to allow walking the devicetree
up. This is required to figure out which PCI domain a device
belongs to.
Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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commit d078ef2152052b5ce8686249dcd05ebd50010889
("soc/intel/cmn/block/pmc: Add previous sleep state strings in log")
used SLP_TYP numbers to map ACPI sleep state value. This incorrectly
printed wrong string for prev_sleep_state during S5.
ex: after a cold reset the previous sleep state printed was
[DEBUG] prev_sleep_state 5 (S3)
This patch corrects this by using ACPI sleep state numbers for mapping
the prev_sleep_state values.
TEST=test the logs on google/rex board after cold reset
[DEBUG] prev_sleep_state 5 (S5)
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I9bcdacc4d01a8d827a6abdf9af2b9e5d686ed847
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80144
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Issue: System hang occurred due to unhandled SPI synchronous SMI,
triggered by LOCK_ENABLE bit and WPD assertion.
Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration
to allow the system to handle and clear SPI synchronous SMI.
BUG=b:306267652
TEST=Cold reboot test on 20 google/screebo by ODM, all passed w/o
hang.
Change-Id: Ie1f096f8eda4adcf1627e44afa517b02adddad76
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Move the call into the FSP code to a file in the common AMD FSP code to
isolate the FSP-specific parts of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Since the romstage code is very similar between all AMD non-CAR SoCs,
factor out a common romstage implementation. All SoCs that select
SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so
this Kconfig option can be used to determine whether to make that call.
In the FSP case, amd_fsp_early_init gets called, while in the case of an
implementation that doesn't rely on an FSP to do the initialization,
cbmem_initialize_empty gets called to set up CBMEM which otherwise would
be done inside the FSP driver code. Since only some SoCs call
fch_disable_legacy_dma_io again in romstage right after
amd_fsp_early_init, introduce the new
SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the
SoCs can specify if this call is needed or not.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80083
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Move the call into the FSP code to a file in the common AMD FSP code to
isolate the FSP-specific parts of the code and a preparation to make the
romstage of all non-CAR AMD SoCs common. Without isolating the call into
the FSP-M code, building the common romstage would fail for genoa_poc
due to fsp/api.h not being in the include path.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so
only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is
selected. Other files have FSP-specific parts too, but those will be
reworked in future patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79984
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that
selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that
selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This
will help to separate the FSP-specific from the FSP-agnostic code. The
mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of
SOC_AMD_PHOENIX.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79983
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This options should not be visible on !Intel, !ACPI and !USB4.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia515d52baead9e151533278c33fda9436ee56168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79669
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I00894565efc405a47348236ad7df50071a843487
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77972
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.
Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The boot time is improved by 65ms. (762ms -> 697ms)
BUG=b:320381143
TEST=check timestamps in cbmem
Change-Id: I74191ab8cbefa08b7e296312645ea40b46fabf77
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79991
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Accessing RAM before mmu initialized is time consuming. During mmu
initialization, `mmu_init()` and `mmu_config_range()` write logs to the
console buffer and contribue the extra boot time.
This patch adds a kconfig option to move `mtk_mmu_init()` to
`bootblock_soc_early_init()`. When `EARLY_MMU_INIT` is enabled, mmu is
initialized before `console_init()` ready. So `mmu_init()` and
`mmu_config_range()` won't write logs to the console buffer and save the
boot time.
It saves about 65ms on Geralt with EARLY_MMU_INIT enabled.
Before:
0:1st timestamp 239,841 (0)
11:start of bootblock 239,920 (79)
12:end of bootblock 323,191 (83,271)
After:
0:1st timestamp 239,804 (0)
11:start of bootblock 239,884 (80)
12:end of bootblock 258,846 (18,962)
BUG=b:320381143
TEST=check timestamps in cbmem
Change-Id: I7f4c3c6c836f7276119698c6de362794cf4222a6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This reverts commit acbc4912375085a099c2427def464d6e481f2a90.
Reason for revert: CB:79525 fixes the issue that led to the revert
by not maintaining the heap in the SMM-stored copy of ramstage at all.
Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a mismatch in how PCI memory resources are allocated on Apollo
Lake with the current configuration. While the ACPI code expects
resources to be below PCR_BASE_ADDRESS (i.e. PMAX), the coreboot C code
allocates them above, leading to the following error messages on Linux:
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
pci_bus 0000:00: root bus resource [mem 0x80000000-0xd0000000 window]
pci_bus 0000:00: root bus resource [mem 0x280000000-0x7fffffffff window]
pci 0000:00:13.1: can't claim BAR 14 [mem 0xdeb00000-0xdebfffff]: no compatible bridge window
pci 0000:00:13.1: can't claim BAR 15 [mem 0xdec00000-0xdecfffff 64bit pref]: no compatible bridge window
pci 0000:00:13.1: BAR 14: assigned [mem 0x80000000-0x800fffff]
pci 0000:00:13.1: BAR 15: assigned [mem 0x281300000-0x2813fffff 64bit pref]
Tested on up/squared with Linux kernel version 6.1.0.
Fix this by setting the DOMAIN_RESOURCE_32BIT_LIMIT to PCR_BASE_ADDRESS,
and by moving the UART base address into the expected range.
Thanks to Nico Huber for the help in writing this patch.
Change-Id: I3a805beb47ab4d19cf8dfce0942485e7982861b1
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79957
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The Cavium CN81xx SoC selects ECAM_MMCONF_SUPPORT, but doesn't set a
value for ECAM_MMCONF_BUS_NUMBER which results in it defaulting to 0
which is wrong. Both the Cavium CN8100 SFF EVB and the OpenCellular
Elgon (GBCv2) mainboard specify 32 PCI buses in their Linux devicetree
files, so set the SoC's ECAM_MMCONF_BUS_NUMBER Kconfig option to 32 to
match this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic98381e2cc597cf23af249c71911545692e40f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79931
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- Handle IOAT stacks with multiple domains in soc-specific code
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The PCIE MMCONFIG base address value and size is updated correctly to
access the PCIE config space registers.
TEST=Verified that PCIE enumeration takes place in boot log
and config space registers are accessible.
Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The IOHUBS0 is a data fabric component which has a fabric id value
specific to SOC. Updated the fabric id for glinda SOC.
TEST=Verified that fabric ID is programmed correctly in boot logs.
Change-Id: I91ea7d7e7d9b247cf479471df287ba8c96b83d75
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79830
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As a preparation for the multi PCI segment group support, use
acpigen_write_BBN to generate the _SEG method that returns the segment
group number of the PCI root. Until the multi PCI segment group support
is enabled in coreboot, it will always return 0.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79924
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This makes sure that prefetchable mem64 memory gets allocated above 4G
which allows non prefetchable resources to be allocated in the tight
window below 4G.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I27d4f9ce91c12ed4ab3b2f18f2a92b742115d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79058
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that Stoneyridge also reports the GNB IOAPIC on the domain and with
the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we
ca switch over to using this common code on Stoneyridge too.
TEST=The resulting MADT doesn't change on Careena
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4ce71a47827e144c4d4991152101650904901f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Move the GNB IOAPIC resource from being reported in the GNB PCI device
to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the
common AMD MADT code will be able to find the resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The IOAPIC structure that this function created is for the IOAPIC in the
GNB and not the one in the FCH which is called Kern in this SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79883
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to
amdblocks/ioapic.h which is both a more logical place for it to be and
this is also a preparation to use the common AMD MADT code for the
Stoneyridge SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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