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Add support to override SPI ROM fast speed based on board version. This
will allow boards to start at lower speeds during bringup and then
switch to higher speeds after assessing the signal integrity. Also
implement a default no-op override.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.
BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Tracker is a debugging tool, include AP/INFRA/PERI tracker.
When bus timeout occurs, the system reboots and latches some
values which could be used for debug.
Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: I82f8e6e5f8ccb7f8246cae45a01a3ddd5f2966f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58244
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tracker is a debugging tool, include AP/INFRA/PERI tracker.
When bus timeout occurs, the system reboots and latches some
values which could be used for debug.
Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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For 1 bit long bit fields an unsigned type should be used. In this case
uint32_t is used instead of a generic unsigned int for both consistency
reasons with the rest of the file and to clarify that the bits will be
packed into a 32 bit memory location.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add a space before the `*/` C-style comment ending.
Change-Id: Ic8928286c8237808b9e380e4393078792589615d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology. The OS is informed to reduce latency for upstream
ports while connecting USB4/TBT devices.
BUG=b:199757442
TEST=It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Drop overrides from `soc_fill_fadt` that do not differ from what common
ACPI code already sets.
Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reference: Intel doc#558579 rev2.2
Change-Id: Iab5dca6eb42abc00bc7da33f640350e994f0bd02
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Tested by adding gfx register on system76/gaze16 and booting Windows.
Display settings has a brightness setting, and can change the brightness
level.
Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Select HAVE_EXP_X86_64_SUPPORT.
Tested on prodrive/hermes: Boots into Linux.
Change-Id: I033ccd5dc793b637a2ac4271b450335464564885
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC
code sets a GPE0 block size of 4 byte length instead of 32 byte.
The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit
instead of 256 bit).
Drop the overrides and let common ACPI code set the correct values based
on `GPE0_REG_MAX`.
Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When "SpeedStep" is disabled on an Intel Atom C3538,
the maximum CPU clock speed is always 800 MHz(min CPU clock).
Оperating system cannot change the frequency.
Avoid this issue allow "Intel Speed step" technology
for processors that do not have "Intel Turbo Boost".
Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
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Enable common Uart driver on sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Ref link: https://review.coreboot.org/c/coreboot/+/45855
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch skips setting D0I3 bit for all HECI devices by FSP.
BUG=b:200644229
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.
Change-Id: I86d61c49b8f187611efd495712ad901184665f31
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.
BUG=b:200644229
TEST=Verified D0i3 bit is set for all HECI devices prior to booting
to OS.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch creates a helper function in cse common code block to check
the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
CSE_4.
Currently cse common code is only able to read the device state of
`PCH_DEVFN_CSE` CSE device alone.
Additionally, print `slot` and 'func' number of CSE devices in case
the device is either disable or hidden.
BUG=b:200644229
TEST=Able to build and boot ADLRVP-P with this patch where the serial
message listed the CSE devices that are disabled in the device tree
as below:
HECI: CSE device 16.01 is disabled
HECI: CSE device 16.04 is disabled
HECI: CSE device 16.05 is disabled
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch ensures to pass cse device function number as argument for
`set_cse_device_state()` to allow coreboot to perform enable/disable of
D0i3 bit for all CSE devices to put the CSE device to Idle state or
Active state.
BUG=b:200644229
TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is
able to put the CSE device toidle state or active state based on `devfn`
as argument.
Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 5f80e7c764b9a1cb46beeaa490a4f60be04abcd4.
The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
into this patch to satisfy the dependency.
BUG=b:194391185, b:179699789
TEST=reboot stress test guybrush for 50 iterations.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These methods can now be dropped as Dynamic GPIO PM is enabled.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0c7b67b5414d8c80775ab7678ce7b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.
BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.
Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Round the PM Timer emulation frequency multiplier to the closest value
to increase precision.
Test: compared hexdumps of CML binaries for the expected result:
before: 0x262E8B51, after: 0x262E8B52
Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57943
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ltiming and clock_div are not support for MT8173, so we separate them
to weak function: mtk_i2c_dump_more_info()
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. The original algorithm for I2C speed cannot always make the
timing meet I2C specification so a new algorithm is introduced
to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
the original implementation was fixed at fast mode (400Khz).
So the mtk_i2c_bus_init is now also taking an extra speed
parameter.
There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1
BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
at 100/300/400/500/800/1000Khz.
Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures all attempts to read CSE BAR is performing PCI config
space read and returning the BAR value rather than using cached value.
This refactoring is useful to read BAR of all CSE devices rather than
just HECI 1 alone.
Additionally, change the return type of get_cse_bar() from `uintptr_t`
to `void *` to avoid typecasting while calling read32/write32 functions.
BUG=b:200644229
TEST=Able to build and boot ADLRVP where CSE is able to perform PCI
enumeration and send the EOP message at post.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
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Move MILLIWATTS_TO_WATTS macro in power_limit header file
so all other files can use the same macro.
BUG=None
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add PMC IPC commands information for FIVR control functionality
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.
[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The value printed is the EPC (Enclave Page Cache) status, but the printk
statement refers to it as `ECP status` instead. Fix the typo.
Change-Id: Iba0a6013f2c537072dd7aa8266f2be3c5b0963ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58038
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Build and boot brya
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
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Append `_MS` for miliseconds and `_US` for microseconds to HECI timeout
macros to improve the code readability.
Change-Id: Ic7f18f07ecaabb3e43356f372d15d18be083464b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across
various warm reboots.
This patch ensures late sending EOP msg when function disabling of CSE
is no longer a requirement.
BUG=b:200644229
TEST=Able to save ~30ms+ of boot time
Without this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,248,328(61,954))
With this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,231,660 (2,754)
Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch ensures soc_finalize() is getting called at the entry of
BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT.
The purpose of this change is to accommodate more time to push out
sending CSE EOP messages at post.
BUG=b:200644229
TEST=coreboot serial log suggests soc_finalize() is getting called
as part of the BS_PAYLOAD_BOOT entry.
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms
Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Prior to coreboot sending EOP messages during post, it's important to
ensure that CSE is not in Idle state. In case CSE is in Dev Idle
state (which means D0I3 bit is set), reset this bit before sending
EOP command.
This patch ensures coreboot has provision to send CSE EOP messages even
after the FSP Notify phase without any delays waiting for the device
to respond or timeout.
BUG=b:200644229
TEST=Able to send CSE EOP message even after FSP Notify phase.
Attempting CSE EOP msg sending post FSP notify without this code change
causes `timeout` issue as below:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
HECI: timed out reading answer!
HECI: Failed to receive!
HECI: receive Failed
HECI: EOP send/receive fail
ERROR: Failed to send EOP to CSE, 2
cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3:
0x20
VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc
Saving nvdata
board_reset() called!
full_reset() called!
Attempting CSE EOP msg sending post FSP notify with this code change
is `successful` as below:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch ensures APIs that are responsible for CSE device state
transition between active to idle and vice-versa are available
publically for other modules/boot stages to consume.
BUG=b:200644229
TEST=Able to build and boot ADLRVP-P.
Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I3677b4e545599d00a4ba16464836834febc2d1a5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58024
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These platforms no longer use reg-script. Drop unneeded select.
Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.
Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.
Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The current names of the PMC init/enable callbacks are very confusing.
Rename them.
Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL.
Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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This CL adds support for new ADL-M graphics Device ID 0x46c3.
TEST=boot to OS
Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).
BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.
Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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The UPDs for PM power cycle duration and SLP_* signal durations are all
identical to Tiger Lake, so add similar support, but use enums instead
of comments to represent the durations symbolically.
BUG=b:184799383
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These methods are never used in the code. Drop them.
Change-Id: If5568b494f821d2647ada5ae845bcd015708520e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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These fields are never used in the code. Drop them.
Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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This field is never used in the code. Drop it.
Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
BUG=b:192429713
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current MRC binaries for Bay Trail are always ELF files. Always
adjust the position in CBFS using the ELF header regardless of file
names. Without adjusting the position, the system hangs right after
calling into MRC.
TEST: MRC position in CBFS does not change for bostentech/gbyt4.
Change-Id: I74e1246a5fac3f3649be9842ff13c2fc70f72a20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57989
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This file does not exist in the coreboot tree. One should place this
file in the `site-local` subdirectory and specify the paths by means
of `site-local/Kconfig`.
Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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mb_set_up_early_espi should only be called when
SOC_AMD_COMMON_BLOCK_USE_ESPI is selected.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable CCP DMA use in PSP verstage. This helps to reduce the boot time.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement
in the boot time.
Before CCP DMA:
508:finished loading body 898,286 (287,576)
Total Time: 2,146,182
After CCP DMA:
508:finished loading body 853,627 (240,061)
Total Time: 2,110,117
Cq-Depend: chrome-internal:4116566
Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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PSP verstage can access the boot device either in Programmed I/O mode or
DMA mode. Introduce a boot device driver and use the appropriate mode
based on the SoC support.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush.
Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.
BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.
Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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The Always On Always Connected block is referenced as AOAC in the code,
so add that acronym in the comment and change the "Connect" to
"Connected".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.
Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This change replaces the device tree walks with device pointers by
using alias for tcss_usb3_port* devices.
Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change add MaxDramSpeed for variants usage to config dram speed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.
This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Explicitly point out that gpio_configure_pads_with_override will ignore
GPIOs that are only in the override configuration, but not in the base
configuration.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some headers in vendorcode are still needed but the UPD definitions
can be taken from the FSP repo.
Change-Id: I7bb96649ecba9d313cfce50af202aabcf610680f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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coreboot expects different names for FSP UPDs so use some CPP to make
it happy.
Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reference: Intel doc# 633935-005 and 547817 rev1.5.
Change-Id: I38c20288a9839f8c3cf895f7b49941387bdca5e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Reference: Intel doc# 631120-001.
Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Reference: Intel doc# 341081-002.
Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add NMI_EN and NMI_STS registers, so NMI interrupts can be used.
References:
- XEON-SP: Intel doc# 633935-005 and 547817 rev1.5
- ICL-LP: Intel doc# 341081-002
- TGL-LP: Intel doc# 631120-001
- TGL-H: Intel doc# 636174-002
- JSL: Intel doc# 634545-001
- EHL: Intel doc# 636722-002
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
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There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add
it, so the group index calculation for GPI/SMI/NMI results in the
correct value.
Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c
Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all dedede variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for cret:
util/spd_tools/bin/part_id_gen \
JSL \
lp4x \
src/mainboard/google/dedede/variants/cret/memory \
src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt
For cappy, the Makefile.inc was manually modified to use the new
placeholder value.
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/dedede -a -x --timeless
Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all volteer variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for voema:
util/spd_tools/bin/part_id_gen \
TGL \
lp4x \
src/mainboard/google/volteer/variants/voema/memory \
src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/volteer -a -x --timeless
Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all brya variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for anahera:
util/spd_tools/bin/part_id_gen \
ADL \
lp4x \
src/mainboard/google/brya/variants/anahera/memory \
src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using: abuild -p none -t google/brya -a -x --timeless
Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Move existing UART driver from sc7180 to common folder.
This implements UART driver for QCOM SoC's
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Before this patch, gpio_configure_pads_with_override called
program_gpios once for each GPIO that needed to be configured which
resulted in base_num_pads - 1 unneeded master_switch_set/
master_switch_clr sequences for the gpio_configure_pads_with_override
call. Instead implement gpio_configure_pads_with_override as the more
generic function and program_gpios as a special case of that which
passes an empty override configuration and override pad number to
gpio_configure_pads_with_override.
TEST=GPIO configuration and multiplexer register values are the same for
all GPIOs on google/guybrush right before jumping to the payload before
and after the patch.
Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Earlier generation platform used `HeciEnabled` chip config (set to 0)
and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at
the end of the post. `HeciEnabled` chip config remains enabled in all
latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig
selection from SoC Kconfig as CSE remains default enabled.
BUG=b:200644229
TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device
is listed with `lspci`.
Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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In this file bool, uint8_t and uint32_t are used, so include types.h
directly to have those types defined instead of relying to have those
included indirectly via amdblocks/gpio_banks.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This implements the SPI driver for the QUP core.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I7e5d3ad07f68255727958d53e6919944d3038260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This implements qup spi driver for qualcomm chipsets
Rename header file names for trogdor to prevent breakage.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I2f2b25b6661fcd518f70383da0c7788c5269c97b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55953
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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copy existing I2C driver from /soc/qualcomm/sc7180 to common folder.
This implements i2c driver for qualcomm chipsets
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common qup driver in sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I0e9049557ff63898037210e72333e1739ab62413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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