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2023-03-20soc/amd/picasso: introduce and use pstate_msr bitfield structFelix Held
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. TEST=The coreboot-generated SSDT containing the P state packages stays identical on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8dc293351f9941cfb8a9c84d9fb9a4fd76361d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-20soc/intel/meteorlake: Enable GPIO IOSTANDBY configurationSubrata Banik
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. TEST=Able to build and boot google/rex. GPIO debug print is showing GPIO PAD config DW1 bit[14:17] are getting programmed. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-20soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk
Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/mtl: Choose serial msg `log_level` based on DIMM countSubrata Banik
This patch modifies the serial msg log_level at runtime to highlight an ERROR if the DIMM count is zero. It would help to draw the attention while parsing the serial msg and catch any underlying issue. TEST=Able to see ERROR msg while booting google/rex with FSP v3064 Without this patch: [DEBUG] 0 DIMMs found With this patch:     [ERROR]  No DIMMs found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17intelblocks/vtd: Add VT-d block with DMA protection APIMichał Żygowski
Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-17qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLibSudheer Kumar Amrabadi
This patch passes a hint flag to QcLib on Lazor boards to tell it to limit the DDR frequency for certain memory parts (8GB Hynix) to work around a board-specific stability issue. BRANCH=trogdor BUG=b:267387867 TEST=Validated on qualcomm sc7180 development board Change-Id: I45915cf93d2a57ff0c9710f2ac36dfb665eff1c6 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-15soc/amd/mendocino: MP2 firmware isn't needed in the RO imageMartin Roth
The MP2 firmware doesn't do anything useful when booting into recovery mode, so don't include it in the RO image if vboot is enabled. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5afbf7e9e730e6951c416f3a3ca75f69a22099cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/73660 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/amd: Print amdfwtool debug info if V=1Martin Roth
When doing coreboot builds, we can set V=1 to see all of the make info printed as the compile is happening. Use this flag to set the debug flag for amdfwtool so it doesn't have to be enabled separately. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5b05cbc9f9b540a174db479822af657cf35733de Reviewed-on: https://review.coreboot.org/c/coreboot/+/73658 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-15soc/amd/common: Ignore * in PSP dependency generationMartin Roth
The regex getting rid of lines containing a '*' didn't match anything in any configs, so get rid of it. There's nothing in the amdfwtool dataparse.c file that would match it either. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I05aaf46cfb479cebab9234a47574073335984a5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15soc/amd/common: Update PSP dependency generationMartin Roth
After adding the ability to add paths into the amdfw.cfg file for the amdfwtool, the dependency generation needs to be updated to not add the firmware location in front of those values. This also allows us to filter out the MP2 binaries as dependencies based on whether or not the Kconfig value is set. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a9b9c8246808dc60020a32a7d9d926bc5e57ccd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-15soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/intel/elkhartlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/coffeelake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/alderlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/mediatek/mt8186: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse BRANCH=corsola Change-Id: I9ab35d82e57f43bac99fa8bd7bb69fcf52250311 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73705 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15soc/mediatek/mt8188: Shut down PMIC on power key long pressSen Chu
Currently on power key long press, PMIC will be reset. It would cause an unwanted reset pulse in the power-off sequence. To match expected sequence, change PMIC behavior to "force shutdown". BUG=b:271771606 TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse Change-Id: I1626892fd582dfab8fe1c1ede1da00549bc97142 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73704 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-13soc/intel/meteorlake: Enable early caching of TOM regionSubrata Banik
Intel Meteor Lake decides to enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM` config. TEST=Able to build and boot google/rex to ChromeOS and reduce the boot time by 77 ms. Without this patch: 950:calling FspMemoryInit 936,811 (19,941) 951:returning from FspMemoryInit 1,041,935 (105,123) With this patch: 950:calling FspMemoryInit 905,108 (20,103) 951:returning from FspMemoryInit 964,038 (59,929) Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/sa: Store TOM into the CMOSSubrata Banik
This patch uses the IA common code API to store the top_of_ram (TOM) address intonon-volatile space (CMOS). The code logic will update the TOM address in CMOS NVS if the `top_of_ram` address is calculated differently in any boot and also takes care of caching the updated range. TEST=Able to build and boot google/rex to ChromeOS. First boot: Before calling into FSP-M [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid ... [DEBUG] tom_table invalid signature [DEBUG]  top_of_ram = 0x76000000 [DEBUG] Updated the TOM address into CMOS 0x76000000 On consecutive boot:Before calling into FSP-M: The TOM region is already cached. [DEBUG]  0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB [DEBUG]  0x00003ffffff80800: PHYMASK0: Length  = 0x0000000000080000, Valid [DEBUG]  0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB [DEBUG]  0x00003ffffffc0800: PHYMASK1: Length  = 0x0000000000040000, Valid [DEBUG]  0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP [DEBUG]  0x00003fffff000800: PHYMASK2: Length  = 0x0000000001000000, Valid [DEBUG]  0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP [DEBUG]  0x00003fffff800800: PHYMASK3: Length  = 0x0000000000800000, Valid [DEBUG]  0x0000000075000005: PHYBASE4: Address = 0x0000000075000000, WP [DEBUG]  0x00003fffff000800: PHYMASK4: Length  = 0x0000000001000000, Valid Change-Id: I2569495570652c488096f6a29f58dd8f0103af9d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13soc/intel/cmn/tom: Cache TOM region earlySubrata Banik
This patch implements a module that can store the top_of_ram (TOM) address into non-volatile space (CMOS) during the first boot and use it across all consecutive boot. As top_of_ram address is not known until FSP-M has exited, it results into lacking of MTRR programming to cache the 16 MB TOM, hence accessing that range during FSP-M and/or late romstage causing long access times. Purpose of this driver code is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot google/rex to ChromeOS. Without this patch: 950:calling FspMemoryInit               936,811 (19,941)   951:returning from FspMemoryInit        1,041,935 (105,123) With this patch:  950:calling FspMemoryInit               905,108 (20,103)   951:returning from FspMemoryInit        987,038 (81,929) Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-13soc/amd/phoenix/mca.c: Remove excess MCA bank namesFred Reitberger
Documentation and hardware differ in the number of MCA bank names, so remove the excess ones to prevent a "CPU has an unexpected number of MCA banks!" warning message. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I75a2348561833f3f19181b4f30a6971ecb317899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-13soc/amd/common/block/cpu/update_microcode: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the microcode update can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51c84164e81477040a4b7810552d3d65c0e3656b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-13soc/amd/common/block/cpu/noncar/write_resume_eip: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, the address of the bootblock_resume_entry can be directly written to the raw value instead of needing to split it into the lower and higher 32 bits and assigning those separately. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I7ebab1784ec592e18c29001b1cf3ee7790615bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-13soc/intel/meteorlake: Select `X86_CLFLUSH_CAR` configSubrata Banik
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b2dce39f82e28cd99ad8621c78bae494c4f16ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/73333 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-10soc/amd/common/psp: Put spl_fuse in separate compilation unitMartin Roth
This separates the SPL fusing function into a separate C file which can be excluded if it is not needed. This allows the psp_set_spl_fuse() function to be made static again as the state of the function will always match the boot_state entry. Move the required #defines to the common header file so they can be used by both psp_gen2.c & spl_fuse.c. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifbc774a370dd35a5c1e82f271816e8a036745ad5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73655 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10soc/amd/common/cpu/smm/smm_relocate: don't assume TSEG is below 4GBFelix Held
Even though right now TSEG will always be located below 4GB, better not make assumptions in the SMM relocation code. Instead of clearing the higher 32 bits and just assigning the TSEG base and per-core SMM base to the lower 32 bits of the MSR, assign those two base addresses to the raw 64 bit MSR value to not truncate the base addresses. Since TSEG will realistically never be larger than 4GB and it needs to be aligned to its power-of-two size, the TSEG mask still only needs to affect the lower half of the corresponding MSR value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1004b5e05a7dba83b76b93b3e7152aef7db58f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10soc/amd/common/block/psp/psp_smm: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5923df84f0eb3a28ba6eda4a06c7421f4459e560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10soc/amd/stoneyridge/monotonic_timer: use raw MSR dataFelix Held
Since mst_t is a union of the struct containing the lower and higher 32 bits and the raw 64 bit value, there's no need to convert the lower and higher 32 bits into a 64 bit value and we can just use the 64 bit raw value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc5d64c74eaabfc4b7834a34410b48f590f78a12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-10xeon_sp: Setup x2apic in SRATNaresh Solanki
Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10soc/mediatek/mt8188: Enable lastbus debug hardwareot_zhenguo.li
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. There are two versions for lastbus: Version 1 for MT8186, and version 2 for MT8188. BUG=b:263753374 TEST=build pass. Change-Id: Ibaf510481d1941376bd8da0168ef17c99a0fb9a2 Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73624 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-10src/soc/amd/phoenix/include/soc/: Update the Data Fabric ID for PhoenixAnand Vaikar
Change-Id: I078b57825377f97f9f5f2b607fa134e3a67e9685 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09soc/amd/common/cpu: move get_threads_per_core from noncar to common codeFelix Held
The get_threads_per_core function isn't specific to the non-CAR CPUs and also applies for Stoneyridge and even for family 16h model 30h outside of soc/amd, so move it from the non-CAR-specific cpu.c file to the common AMD SoC cpu.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I05946f163112ff93f33139f6c43fed5820fd0a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-09soc/amd/common/cpu/Kconfig: use Cxxx as CPU string for all non-CAR SoCsFelix Held
Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it being what the AGESA reference code uses. We initially relied on the AGESA/FSP generated SSDT for the P- and C-state support before we had a native implementation for this in coreboot. The Cxxx naming scheme can also be used for the other AMD SoCs except Stoneyridge which is pre-Zen and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of using Cxxx instead of CPxx is that the Cxxx scheme supports systems with more than 256 CPU threads. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD deviceJonathan Zhang
For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus() returns NULL. Therefore use pci_s_write_config32() instead. Move lock_pam0123() from finalize.c to util.c, to be together with unlock_pam_regions(). Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-09soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specificsJonathan Zhang
Intel SPR-SP has its specific way to get the bus number of ubox. Move the current implementations to CPX-SP and SKX-SP folders. Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-09soc/amd/cezanne: Set up SoC-specific XHCI definitionsRobert Zieba
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BRANCH=guybrush BUG=b:186792595 TEST=builds Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/amd/cezanne: Update XHCI GPE to use constantRobert Zieba
The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin device and verified that XHCI events string use GPE 31. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69917 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/amd/mendocino: Set up SoC-specific XHCI definesRobert Zieba
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI. BUG=b:186792595 TEST=builds Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67938 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/amd/mendocino: Update XHCI GPE to use constantRobert Zieba
The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BUG=b:186792595 TEST=Ran on skyrim device and verified XHCI GPE setting. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/69916 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09soc/amd/common/xhci: Add support for logging XHCI wake eventsRobert Zieba
AMD SoCs currently only log the GPE# when an XHCI controller wakes the system. Add code to log XHCI wake events to the elog. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-09soc/intel/broadwell/gma: don't unconditionally remap all GPU PCI IDsFelix Held
This fixes the case where a Broadwell CPU is combined with an AMD or NVIDIA GPU would result in using the Broadwell GPU VBIOS file from CBFS for the discrete GPU too. A further improvement would be to use a list of the Intel iGPU PCI IDs like it is done in the Skylake code. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3eb50cb9a0539255d50e5cd8163f10c3a062cc4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73611 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09soc/intel: Update API name `pmc_send_bios_reset_pci_enum_done`Subrata Banik
This patch updates PMC API name from `pmc_send_pci_enum_done` to `pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done is also set along with PMC enumeration being done. BUG=b:270942083 TEST=Able to build and boot google/rex. Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-08soc/amd/common/psp: Check more error bits before SPL fusingMartin Roth
This adds checks for three more error bits before requesting that the SPL fuses are updated. - While I'm here, I'm adding the include of types.h which was previously done through other include files, but should be done independently. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I87a7d40850c4e9ddbb2d1913c1588a919fdb29d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-08soc/amd/common/psp: Only set SPL fuses if an SPL file is presentMartin Roth
Use the presence of an SPL (Software Patch Level) file to trigger the function that reads and writes the SPL fuses. The current Kconfig option will be used to decide to write the fuses. This allows us to see the state of the SPL update bit which determines whether or not SPL fusing is allowed and needed before enabling the fusing. - Refactor a bit to prepare for following changes. - Update phrasing Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I7bd2798b984673a4bd3c72f3cab52f1c9a786c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-08soc/amd: factor out ACPI_SSDT_PSD_INDEPENDENT to common AMD ACPI KconfigFelix Held
Now that the code using the ACPI_SSDT_PSD_INDEPENDENT Kconfig symbol is moved to soc/amd/common/block/acpi/cpu_power_state.c, also move the Kconfig symbol to the Kconfig file in this directory. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ide18111df38d4e9c81f7d183f49107f382385d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: introduce get_cstate_io_baseFelix Held
Introduce the get_cstate_io_base helper function that write_cstate_entry can call directly to get the C state control IO base address instead of having get_cstate_info pass this Io address to each write_cstate_entry call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I4cc80ded0a2fbc2dee9ca819e86284d9ffd58685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held
The bit position of the P state enable bit in the 8 P state MSRs is identical for all AMD chips including the family 16h model 30h APU that lives outside of soc/amd. The other bits in those 8 MSRs are more or less family- and model-specific. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08soc/amd/*/acpi: factor out common get_pstate_info implementationFelix Held
The implementations of get_pstate_info of Picasso, Cezanne, Mendocino, Phoenix and Glinda are identical, so factor it out and move it to the common AMD SoC code. The SoC-specific get_pstate_core_freq and get_pstate_core_power functions remain in the SoC-specific code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe0494f1747f381a75b3dd71a8cc38fdc6dce042 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/*/acpi: factor out common generate_cpu_entries implementationFelix Held
With the exception of the generate_cppc_entries call, the implementations of generate_cpu_entries of Picasso, Cezanne, Mendocino, Phoenix and Glinda are identical, so factor it out and move it to the common AMD SoC code. Since all SoCs that support CPPC already select the SOC_AMD_COMMON_BLOCK_ACPI_CPPC Kconfig option, this can be used to only call generate_cppc_entries for platforms where it is available. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71323d9d071b6f9d82852479b60dc56c24f2b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/73504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/phoenix: Allow the amdfw.rom to be split into two partsZheng Bao
Split the big PSP FW data into two parts, head and body. The head needs to be located at original specific location. The body address is more flexible. So the big body will not cover other needed FWs like EC. Give the body a specific named AMDFWBODY, which should be defined in flashmap. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Ia8b318f71632a2c9b97ce67486374dc24d23e63e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/stoneyridge/romstage: pass C state control IO base addressFelix Held
Instead of hoping that the default the C state control IO address in binaryPI won't interfere with any other IO space usage in coreboot, assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform config structure element to make sure that binaryPI will use a known address for the IO port based C state control. binaryPI will write this address to the MSR_CSTATE_ADDRESS and will then also use these IO ports in the _CST packages in the PSTATE SSDT, so changing this won't cause a mismatch between those two. The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on Careena is 0x1770, so this didn't collide with any other IO space registers, but it's still much better to tell binaryPI which exact IO addresses to use. TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in the _CST package entry for the second C state which are both the expected values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/glinda/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. The actual values in cstate_cfg_table haven't been checked against the reference code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5157fc031c5b19d8633132222520f582620208c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/phoenix/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. The actual values in cstate_cfg_table haven't been checked against the reference code yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4f5743dd2e4dfdfeb3ffb2e9b964bdc75c84e6c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/mendocino/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3669c66094f0137081888ebdd1af838e2ea269b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/cezanne/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id97fcb74ff3d48994a3181d9c31cbbeb5a76c60a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/picasso/acpi: rework C state info table handlingFelix Held
Rework the way the C state info is generated before it gets passed to acpigen_write_CST_package in generate_cpu_entries by separating the data from the code. For this, the newly introduced common get_cstate_info function is used. Separating the data from the code will eventually allow moving generate_cpu_entries to the common AMD code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6bd8879ce5968b24893b43041be98db55a4c3c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: use definition for bit_offsetFelix Held
Instead of using a magic constant in the bit_offset field of the C state resource for the C1 state that's entered via the MWAIT instruction, use the existing ACPI_FFIXEDHW_CLASS_MWAIT define. This value is checked by acpi_processor_ffh_cstate_probe in the Linux kernel. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9edc681efab15b5ceba91c8105f7dc6d687d8be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-08soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helperFelix Held
Introduce the get_cstate_info helper function that populates the caller- provided cstate_values array with the data returned by the SoC-specific get_cstate_config_data function. From the array get_cstate_config_data returns, only the ctype, latency and power fields are used, so the rest can be left uninitialized. Those 3 fields are compile-time constants. For each entry, write_cstate_entry will generate the corresponding resource information from the given data. In the C1 case where ctype is 1, the state is entered via a MWAIT instruction, while the higher C states are entered by doing an IO read from a specific IO address. This IO address is x - 1 bytes into the IO region starting at MSR_CSTATE_ADDRESS for the Cx state. So for example C2 is entered by reading from the C state IO base address + 1. This resource information is generated during runtime, since the contents of MSR_CSTATE_ADDRESS aren't necessarily known at compile-time. MAX_CSTATE_COUNT is introduced so that the caller can allocate and pass a buffer with space for the maximum number of C state entries. This maximum number corresponds to the number of IO addresses the CPU traps beginning from MSR_CSTATE_ADDRESS. In practice, it's unlikely that more than 3 or maybe 4 C states will be available though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-07soc/intel/xeon_sp: Add PM definition for SPR-SPDavid Hendricks
Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-07soc/intel/adl: Increase MAX_CPUS to 32 for RPLTim Crawford
Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads. Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73514 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-07soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDTFelix Held
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the scope for the CPU objects and patching this SSDT in coreboot to use the \_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the \_SB_ scope instead by setting the late platform configuration option ProcessorScopeInSb to true. TEST=Careena still boots and Linux doesn't show any ACPI errors with this patch applied. With only patch_ssdt_processor_scope removed, but the ProcessorScopeInSb option not set, Linux will complain that it can't resolve the \PR.P00x symbols. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If88820a0f5df923f129e2e3b5335f5f0e38ee7f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-06soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUsFelix Held
The legacy ACPI CPU control registers in IO space where the first 4 IO locations control the CPU throttling value don't exist any more on the Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS in set_cstate_io_addr which will cause accesses from the 8 IO addresses beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads from those IO addresses will cause the CPU to enter low C states. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/include/iomap: add comment about ACPI IO assignmentFelix Held
Finally figured out why ACPI_GPE0_BLK only being 4 bytes after ACPI_CPU_CONTROL won't work and its due to the CPU trapping 8 IO addresses from ACPI_CPU_CONTROL on for C state control. This is set up in set_cstate_io_addr by writing the ACPI_CPU_CONTROL value into MSR_CSTATE_ADDRESS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL defineFelix Held
Picasso and newer don't implement the P_CNT register to control the CPU duty cycle and also trap the C state control IO addresses directly in the CPU, so those won't reach the FCH. This register is unused in the Picasso code and not even defined any more in the Cezanne PPR. The Picasso PPR does define this register, but since it's useless and might even just be a leftover form a pre-Zen CPU generation, drop the define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unnecessary duty_offset/duty_width field writesFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the duty_offset and duty_width FADT field in acpi_fill_fadt for all SoC except Stoneyridge. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib63b24891d44298841153dfc500b030619e1a5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/73421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/picasso/acpi: don't announce unimplemented duty cycle controlFelix Held
Picasso neither has the corresponding P_CNT register implemented nor writes a _PTC ACPI object that would specify the P_CNT register. The Picasso UEFI reference code also sets the duty_width FADT entry to 0. This also aligns the Picasso code with the Cezanne code in this regard. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I74645e5c4e54a2ad6bc7f9e72f5f656027a79860 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unneeded pstate_cnt FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the pstate_cnt FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If3ddb466de1d437361d811e45e328a1dbff02fcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-06soc/amd/*/acpi: drop unneeded mon_alrm FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the mon_alrm FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabb5fc7367f1e4e7acea1a58abdb643fc46ca776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05soc/mediatek/mt8188: Add bus protection for audio/video mtcmosgarmin chang
Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang@mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05soc/intel/alderlake: Hook up ucode for RPL-P/H/UTim Crawford
Hook up microcode from 3rdparty repo for: - 06-ba-02 (CPUID signature: 0xb06a2) Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-04soc/amd/mendocino: Add STT support for dptc tablet modeChris Wang
Add stt settings for dptc tablet mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the clamshell/tablet mode. Run the WebGL aquarium with 5000 fish and verify that there is no power drop peak. Change-Id: Ib4aad3af8761b20084717b15a462edf4704b83cc Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73205 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-04xeon/spr: Set ACPI CPU string for 12bitNaresh Solanki
On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-04soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03soc/amd/cezanne/graphics: simplify map_oprom_vendev implementationFelix Held
Phoenix' implementation of map_oprom_vendev uses this simplified implementation, so port this back to Cezanne too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0aa3a0fed37c6cba15a668ada639f5fd0c212d2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73387 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-03soc/intel/xeon_sp: Fix CBMEM corruptionPatrick Rudolph
On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-02amdfwtool: Change .rom.efs to .rom and .rom to .rom.bodyZheng Bao
To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-02soc/intel/alderlake: Hook up ucode for RPL-S/HX B0Tim Crawford
Hook up microcode from 3rdparty repo for: - 06-b7-01 (CPUID signature: 0xb0671) Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13), which has an i9-13900HX. Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-02soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC supportChris Wang
Add a new parameter STT_ALPHA_APU' for each DPTC mode. BUG=b:257149501 BRANCH=None TEST=Check if the STT value matches the expected setting. Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2023-03-02soc/mediatek: Add config to control DRAM scrambleXi Chen
The DRAM scramble feature enhances DRAM data protection. When it's enabled, the written DRAM data will be scrambled and hence can prevent the data from being hacked. This feature would make debugging more difficult (for example ramoops would be lost after reset). Therefore, add a new config to allow enabling or disabling the feature from coreboot, without having to maintain two versions of the DRAM calibration blob. BUG=b:269049451 TEST=build pass and check scramble enable or disable successfully Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: Ib4279bc1cc960fae9c9f5da39f4448a5627288d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-01soc/intel/xeon_sp/spr: Select DISABLE_ACPI_HIBERNATE to remove S4 stateTim Chu
Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE to remove S4 state from available sleepstates. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-01soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeSean Rhodes
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0. Remove the incorrect comment and make the UPD configurable from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-28soc/amd: introduce and use PSTATE_MSR macroFelix Held
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-28soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usageFelix Held
The latency values in the _CST package override the values in the p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino, Phoenix and Glinda generate_cpu_entries generates the _CST packages for each CPU device. The coreboot code for Stoneyridge doesn't generate _CST packages for the CPU objects, but those are provided via the PSTATE SSDT binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI tables. The AGESA reference code also sets those two FADT entries to the equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED so this also matches the AGESA behavior. From the ACPI 6.4 spec: "Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT." Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-28soc/amd/stoneyridge/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
IRQ9 is used as ACPI SCI IRQ, so add a define for that and use it in the code like it is also done in the other SoCs in soc/amd. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddb51d70c15ab1d7088f62b61e22510bd1b30b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73320 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso/acpi: use ACPI_SCI_IRQ definitionFelix Held
Since there's a define for the ACPI_SCI_IRQ 9, use the define instead of a magic number in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c8f62929f3f66192698e10826d10329ef3d8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73319 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso,stoneyridge/acpi: drop unneeded res2 FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the res2 FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa69ae61bea82acf66e7210c4103ef48e36dbdd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>