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2024-10-11soc/intel/xeon_sp: Revise IIO domain ACPI name encodingShuo Liu
GNR/SRF supports up to 18 logical IIO stacks. Revise IIO domain ACPI name encoding in below form to support GNR/SRF, prefix (16 bit) | socket (3-bit) | stack (5-bit) Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-11soc/amd/common/block/psp/Kconfig: drop some 'default n'Felix Held
Since the Kconfig default for boolean options is already 'n', there's no need to add that default to the option. Still kept the 'default n' for the 3 options that result in fuses inside the SoC to be burnt (PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected by default more clearly. Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-10-11soc/amd/common/psp_smi_flash: add RPMC command-specific data structuresFelix Held
Add the data structures used for the command buffers for the PSP SMI commands to increment and request the state of the monotonic counters in the SPI flash. These data structures are specific to the PSP SMI mailbox interface and not the data structures from the RPMC specification. The AGESA code was used as a reference. Change-Id: I8bc8ff4cf9b7ebd0e034f040dde2db8385bb8f79 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/alderlake: Fix PEG0 IRQ routingSean Rhodes
PEG0 should be set to PCI_INT_D, not PCI_INT_A. This fixes: pcieport 0000:00:06.0: can't derive routing for PCI INT D pcieport 0000:00:06.0: PCI INT D: not connected PEG1 should also be PCI_INT_B. Tested on `starbook_adl` with Ubuntu 24.04 by running SSD benchmark with GNOME disks and suspend. Change-Id: I0f37bb9ac8572d7335084a20fceca6977a491498 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84619 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CNIP MethodSean Rhodes
This method is used to provision the CNVi, and ensure that it is in the correct state. Intel document #559910 details this. Change-Id: Id8a36a09c7beaf3ba8b29d3276bd9dc59420dab5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83713 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add CFLR MethodSean Rhodes
This method is used to limit frequencies on CNVi. Intel document #559910 details this. Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add power related methodsSean Rhodes
Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must exist to avoid a BSOD on Windows. Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvw: Add GPEH MethodSean Rhodes
Add a general purpose handle to allow CNVi to be notified of state changes. Intel document #559910 details this. Change-Id: I36c98c525c99fb2b7b5ebd8b0e392e6626e97290 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83710 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11soc/intel/cnvi: Add PRR method for CNVi ResetSean Rhodes
Add a _PRR method that the OS can use to reset the wireless. This is only used for integrated solutions and depends on the CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new ACPI is added, the behavior of existing boards won't be changed unless they configure the accompanying Bluetooth device. Intel document #559910 details this. Change-Id: I25e8462780badcad88b13052a6eb282c83af5def Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add _S0W to ensure CNVi isn't put into D3 ColdSean Rhodes
All CNVi modules, integrated or dedicated only support D3 Hot so add _S0W to limit the sleep state. Intel document #559910 details this. Change-Id: I1541cebc022adc927a9cd883500320e9ef82359f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CWAR FieldsSean Rhodes
These fields are used to monitor events on CNVi. Intel document #559910 details this. Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-11soc/intel/cnvi: Add CNVW OpRegionSean Rhodes
The CNVi driver is relatively basic in coreboot and most noticeably, recent Linux kernels flag that lack of a _PRR method, which is used to reset WiFi and Bluetooth. This patch series adds methods recommended by Intel in document #559910. This patch defines an OpRegion for CNVi, for both integrated and dedicated solutions. Change-Id: Idd2ff93fb65c40f656804d96966e1881202ccb56 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-11soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetreeSean Rhodes
Hook up CNVi Bluetooth UPDs to the devicetree. Set CnviBtCore to `true` so the current behaviour is not changed. Change-Id: Ic5640c23af3ce30498be814a6d7ce56988653b25 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84596 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09soc/amd/common/psp: add and call PSP SMI SPI RPMC function stubsFelix Held
In the case where the x86 owns the SPI controller and the RPMC feature is used, the PSP will send an SMI to the x86 side for it to send the RPMC increment monotonic counter and RPMC request monotonic counter commands to the SPI flash and return the result to the PSP. Add stubs as handlers for those two PSP SMI commands. Change-Id: If6091d2b0002f817922cac4cba373f0f981b646e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84702 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ana Cabral
2024-10-09soc/intel/{tigerlake,alderlake}: Correct FSP config rather than assertingSean Rhodes
Meteor Lake handles a misconfigured devicetree better than Alder Lake and Tiger Lake; it throws a warning and corrects the FSP config rather than asserting. Copy that behavior to Alder Lake and Tiger Lake. Change-Id: Ifd768fc31a0a6ef2fa0ae7e890cf0b47a9968d30 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84647 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-09drivers/usb/acpi: Move the CNMT Mutex to USBSean Rhodes
The Intel Bluetooth driver can be combined with either CNVi, or full PCI wireless cards such as the AX210. Move it to the USB code so it can be used by either or. Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/cannonlake: Add missing USB port aliasesMaxim Polyakov
FSP for Comet Lake S allows one to configure 16 USB2 (PortUsb20Enable array) ports and 10 USB3 (PortUsb30Enable array) ports [1, 2]. [1] src/soc/intel/cannonlake/chip.h [2] 3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/FspsUpd.h Change-Id: Ie69543f335be1a69cf0c068335c2e17eebf4c6a9 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-07soc/intel/cannonlake/fsp_params: Rename FSP_S_CONFIG variableMatt DeVillier
All newer Intel SoCs use `s_cfg` as the variable name for a FSP_S_CONFIG struct pointer, so use that for CNL as well to avoid copy/paste errors when applying changes across SoCs which touch the FSP_S_CONFIG struct. Change-Id: I5eadb77f312ad6ad1072bc02adf98d97b1940236 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84653 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/adl to jsl: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84586 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07soc/intel/alderlake: Hook up PCIe Power Management to option APISean Rhodes
Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the option API. This provides users an easy way to disable power saving options that can limit performance. Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-05soc/intel/pantherlake: Add FSP-S programmingJeremy Compostella
FSP-S UPDs are programmed according to the configuration (Kconfig and device tree) in ramstage. BUG=348678529 TEST=Hardware is programmed as desired and Intel Panther Lake reference board boots to UI. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-03soc/amd/glinda/.../iomap.h: Update for glindaMaximilian Brune
Remove TODO after checking the addresses are still valid. source: PPR 57254 Rev 1.59 Table "Address Space Mapping under APB BUS" Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-10-03soc/amd/glinda/include/smu.h: Update mailbox register addressesAvinash Munduru
Signed-off-by: Avinash Munduru <AvinashMunduru@amd.com> Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778 Tested-by: Avinash Munduru <Avinash.Munduru@amd.com> Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84384 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03soc/amd/.../amd_pci_int_defs.h: Update according to datasheetMaximilian Brune
HPET and MISC1/2 and registers are used interchangeably in the datasheets. Add an alias to emphasise that they refer to the same. source: PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list" PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list" PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84574 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03soc/amd/*: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-03soc/intel/pantherlake: Remove soc_info.[hc] interfaceJeremy Compostella
This commit removes the unnecessary layer provided by soc_info.[hc]. It was providing an abstraction which only was resulting in extra function calls without any added value as the returned constants are well identified and could be used directly. More importantly, and this is the actual selling point in my opinion, this extra indirection was preventing the compiler from detecting array overflows. BUG=348678529 TEST=Build is successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6986 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-02soc/intel/cannonlake,skylake: Fix locking SMRAMMichał Żygowski
Intel TXT SINIT required the D_LCK bit set. Although coreboot tries to set it, the bit ws still clear. The D_LCK bit has to be set using I/O CF8/CFC cycle. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-02soc/intel/meteorlake: Correctly set Usb4CmModeSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will timeout. TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-02soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resourcesShuo Liu
On GNR, there are CXL Type-3 memory windows covered under TOHM. The current 4GB to TOHM DRAM reporting doesn't work on GNR. Use MemoryMapDataHob to add high RAM resources as a generic mechanism for GNR and previous generation SoCs. TEST=Build and boot on intel/archercity CRB TEST=Build and boot on intel/beechnutcity CRB (with topic:"Xeon6-Basic-Boot") Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/mt/mt8196/gpio_eint.c: Add assert messageArthur Heymans
This fixes the following warning with clang (18.1.6): src/soc/mediatek/mt8196/gpio_eint.c:259:44: error: '_Static_assert' with no message is a C23 extension [-Werror,-Wc23-extensions] 259 | _Static_assert(ARRAY_SIZE(eint_data) == 293); | ^ | Change-Id: I934b6d7ee8e8a0c204a4e328331c3ff3cd0f07de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84618 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/qualcomm/sc7{1,2}80: Increase early stages size for clangArthur Heymans
Clang builds slightly larger binaries so increase the section. The qcsdi is used for an external blob that is currently not in use so reducing the size is fine for now. Change-Id: Ide01233f209613678c5408f1afab19415c1071be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-10-02soc/intel/pantherlake: Delete duplicated lineJeremy Compostella
BUG=348678529 TEST=Build successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84607 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/intel: Deprecate SoC-specific global reset status configsSubrata Banik
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X` Kconfigs, as they are no longer necessary for handling FSP global reset requests. Previously, these Kconfigs were used to select a specific 32-bit reset status code. However, with the introduction of FSP 2.4 and 64-bit interfaces, the global reset status code can now vary between architectures. To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET` config to a common default value (depending upon most commonly used global reset status code) based on the interface: - 0x40000003 for 32-bit FSP interfaces - 0x4000000000000003 for 64-bit FSP interfaces This default can be overridden if an FSP implementation uses a different status code (for example: Apollo Lake selects different FSP reset status code as 0x40000005). By removing the SoC-specific configurations, this change simplifies global reset handling and ensures compatibility across different FSP versions and platforms. Below table shows the relationship between Platform, FSP and FSP Global Reset Status: +-----------------+--------------+-------------------------+ | Platform | FSP | Global Reset Status | +-----------------+--------------+-------------------------+ | Alder Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Apollo Lake | 32-bit | 0x40000005 | +-----------------+--------------+-------------------------+ | Cannon Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Elkhart Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Jasper Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Meteor Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Sky Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Tiger Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Panther Lake | 64-bit | 0x4000000000000003 | +-----------------+--------------+-------------------------+ BUG=b:347669091 TEST=Verified FSP requested global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. w/ 32-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 40000003 FSPS, status=0x40000003 FSP: handling reset type, status=0x40000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` w/ 64-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 3 FSPS, status=0x4000000000000003 FSP: handling reset type, status=0x4000000000000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-01soc/intel: Correct return type of fsp_get_pch_reset_status()Subrata Banik
The `fsp_get_pch_reset_status()` function returns a FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/common/cnvi: Add CNMT MutexSean Rhodes
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/cannonlake: Fix USB port numbersMaxim Polyakov
It should be in HEX. Change-Id: I15a354bae414ad94a2f76030b3099179022b935c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84546 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01tree: Use boolean for dptf_enableElyes Haouas
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84161 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda: Update pci int defsMaximilian Brune
Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda: Update gpp bridge naming schemeMaximilian Brune
This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30soc/amd/glinda: Update SCI mappingMaximilian Brune
source: PPR #57254 Rev 1.71 Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84381 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda/include/soc/smi.h: Update for glindaMaximilian Brune
It aligns the names in the datasheet with the one in the code. It also removes and adds some. Resource: Document 57254 Chapter 15.3.5 TODO it may very well be that I don't have the full truth, because most of these register just have a different name and some of these names like ESPI seem more recent that for example LPC. Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30soc/amd/glinda: Remove non-exisiting I2C definitionsMaximilian Brune
Glinda doesn't contain I2C4 and I2C5 like Mendocino it was copied from. Remove their definitions. Reference: Document 57254 Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30soc/mediatek/mt8196: Fix timer reset in BL31Jarried Lin
After reboot, the system does not need to serve pending IRQ from systimer. Therefore, clear systimer IRQ pending bits in init_timer(). For that to work, the systimer compensation version 2.0 needs to be enabled. TEST=Build pass and timestamp is not reset in ATF and payload BUG=b:343881008 Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-30soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help textPaul Menzel
regist*re*s → regist*er*s Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-09-28soc/intel/pantherlake: Add FSP-M programmingJeremy Compostella
FSP-M UPDs are programmed according to the configuration (Kconfig and device tree). BUG=348678529 TEST=Memory is initialized successfully and hardware is programmed as desired on Intel pantherlake reference board. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-27soc/intel/pantherlake: Comply with the no typedef coding style ruleJeremy Compostella
As https://doc.coreboot.org/contributing/coding_style.html#typedefs states: "In general, a pointer, or a struct that has elements that can reasonably be directly accessed should never be a typedef". This commit makes the Intel Panther Lake SoC code comply with this by using explicitly `struct soc_intel_pantherlake_config' in the soc/intel/pantherlake code as I have been suggested to for the `fsp_params.c' files. The rule being the rule and consistency across a project matters more than personal preferences. The documentation lists five exceptions and none on them cover the use of `config_t' instead `struct soc_intel_pantherlake' but I believe it does not make the code better for the following three reasons: 1. It is repetitive, make the line longer and the code is in soc/intel/pantherlake so obviously the config_t data structure is the pantherlake soc configuration. 2. It makes re-usability from one generation to another unnecessarily harder. 3. This config_t abstraction is required for and used by some common block code anyway. Hence, we end-up with some code using `config_t' and other using the final structure which break the consistency of the code when the project in looked as a whole. BUG=348678529 TEST=Google fatcat mainboard compiles Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-27driver/intel/ish: Add config to indicate the presence of ISH MAIN firmwareJayvik Desai
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware. The ISH MAIN firmware is located in rootfs, hence we no longer need to store the ISH BUP version in the CSE partition. When this config is enabled, fetching the ISH BUP version from the CSE firmware partition is skipped. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. Enabling this config skips printing the ISH version in cbmem. Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-26soc/amd/glinda/chipset.cb: Add missing devicesMaximilian Brune
Source: Document 57254 Change-Id: I9675d45eba257e52d9a870a4cc153b925267f840 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-26soc/amd/glinda/chipset.cb: Update for glindaSatya SreenivasL
This also updates the mainboards depending on it. Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26soc/intel/ptl: Remove tcss_d3_hot_disable en config structure fieldJeremy Compostella
This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-25vc/amd/opensil: Move openSIL interface declarations to common headerNicolas Kochlowski
The declarations describing interface functions between SoCs and openSIL glue code are common for the stub and Genoa POC, and likely with future SoC openSIL implementations. Therefore, move these out of SoC-specific header files and into vc/amd/opensil/opensil.h. This change facilitates swapping out the stub for the actual openSIL glue code. Change-Id: Icc8783ddb868f9f0c4cd357245604313eadfe531 Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25ssoc/intel/tigerlake: Use boolean for enable_c6dramElyes Haouas
"enable_c6dram" needs only 2 "states" to be clearly defined. C provides "true/false", so use it instead of using unsigned int. Change-Id: Icff1b42ceb2e89cc0b2e7abab6743430c635db7b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84155 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp: Support GNR PCIe root portsShuo Liu
Add device IDs for GNR PCIe root ports so that these devices can be supported by the Xeon-SP PCIe root port driver. Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp/gnr: Enable VMX by FSPJohnny Lin
Configure FSP UPD VMX from Kconfig ENABLE_VMX. Change-Id: I0c03f535b6f93761419657127e791c02e8ee4988 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84327 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/xeon_sp/gnr: Remove duplicated HPET tableLu, Pen-ChunX
Both lpc.c and chip.c will create HPET table. remove hpet_device_ops for avoiding create two HPET table. Change-Id: I32628e98b5c1fac4b72ea3abf755b62847161bec Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-24soc/intel/xeon_sp/gnr: Implement SMM methodsJincheng Li
Change-Id: I578b2c213ff1b33b4ca37e0422f690bedc9f5ba1 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84325 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-24soc/intel/common/block/lpc: Support IBL eSPIShuo Liu
IBL eSPI should be correctly configured by LPC driver so that console input is usable. Change-Id: I77cc6dd67b36035974e7f268d32b8473e8d83483 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-24soc/intel/meminit: Check array sizeArthur Heymans
Work around a GCC LTO bug. Even if no buffer overflow is bound to happen as the soldered down path is taken GCC LTO complains about this. Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-23soc/intel/pantherlake: Disable Total Memory EncryptionJamie Ryu
TME, Total Memory Encryption will be enabled once the feature is fully verified with Panther Lake. Change-Id: I600c8a499df3b8796df35813422d0e89f67cc630 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84418 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-21soc/intel/ptl: Remove usb2_port_reset_msg_en config structure fieldJeremy Compostella
Similarly to what is done in Meteor Lake, the PortResetMessageEnable UPD can be set based on usb2_port[].type_c setting and therefore usb2_port_reset_msg_en is not necessary. BUG=b/348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d57 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84429 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-21soc/intel/ptl: Provide the TCSS port policy setting optionsJeremy Compostella
Each TCSS port can be associated a setting via the tcss_cap_policy device tree field. The setting can be picked within five values listed by this commit. BUG=b/348678529 TEST=fatcat board build tcss_cap_policy[0]=TCSS_TYPE_C_PORT_FULL_FUN Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d56 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-20soc/mediatek/common: Correct eMMC src clk frequency to 400 MHzkiwi liu
Mediatek SoCs start operating at eMMC clock around 3MHz right after power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs under 400kHz. When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and get the division value 128. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/128=3.125MHz. So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz. BUG=b:356578805 TEST=test boot ok; measure eMMC clock ok; no boot time impact Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com> Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-09-20soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block rather than checking if GPE1_STS(0) is '0'. BUG:362310295 TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check that FADT table includes GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Without the flag, boot to OS and check that FADT table does not include GPE1. FADT should have: GPE1 Block Address : 0 GPE1 Block Length : 0 GPE1 Base Offset : 0 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-19soc/intel/mtl: Hook up GMA ACPI brightness controlsJeremy Soller
Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Signed-off-by: Jeremy Soller <jeremy@sysetm76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-19soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMICliff Huang
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0' BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method. Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/84349 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-19soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time ↵Mario Scheithauer
tuning If real-time tuning was enabled, 'PchPwrOptEnable' was set two times with different values. This patch fixes the issue. BUG=none TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-18soc/intel: Move CSE update ELOG to cse_lite.cSubrata Banik
The ELOG for CSE updates was being added in fsp_params.c, but the actual update happens in cse_lite.c. This commit moves the ELOG to cse_lite.c to more accurately reflect where the event is happening. This also removes the need for a sol_type variable in meteorlake/romstage/fsp_params.c. It also helps to avoid redundant ELOG event entry while performing CSE update (due to CSE RO to RW switch dependency). BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo) TEST=Able to see only one instance of ELOG while performimg CSE sync. w/o this patch: elogtool list 0 | Log area cleared | 4088 1 | Kernel Event | Clean Shutdown 2 | Early Sign of Life | MRC Early SOL Screen Shown 3 | Early Sign of Life | CSE Sync Early SOL Screen Shown 4 | System boot | 29 5 | Memory Cache Update | Normal | Success 6 | Early Sign of Life | CSE Sync Early SOL Screen Shown w/ this patch: elogtool list 0 | Log area cleared | 4088 1 | Early Sign of Life | MRC Early SOL Screen Shown 2 | Memory Cache Update | Normal | Success 3 | System boot | 30 4 | Memory Cache Update | Normal | Success 5 | Early Sign of Life | CSE Sync Early SOL Screen Shown Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-09-18soc/intel/ptl: Add SoC ACPI directory for Panther LakeRavi Sarawadi
List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-17soc/intel/alderlake: Enable CRASHLOG for Chrome OSSubrata Banik
Enable the CRASHLOG config option for Chrome OS boards. This allows the Chrome OS crash reporter to collect and analyze crash dumps, aiding in debugging and improving system stability. TEST=Able to build and boot google/brox Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-17Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"Subrata Banik
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-16soc/amd/common/psp/psb: add missing newline in debug messageFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I794899fa55b510e6f39dadc1a831b86389ab31ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/84355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-09-14mainboard/intel/avenuecity_crb: Update full IIO configurationShuo Liu
Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13mb/google/brox: Fix booting to kernel without batterySowmya Aralguppe
When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-13soc/intel/xeon_sp/gnr: Support full IIO UPD configurationsShuo Liu
Change-Id: Iebfadffd2da83992af983b8c0dfe2706f81eb728 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84317 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Move CPU ID definition to common headerJincheng Li
Change-Id: I816c6f68840c122fbc37085e31a1b0368a819f4a Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84313 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Enlarge MAX_CPUS to 512Jincheng Li
GNR-AP supports up-to 128 cores/256 threads per socket. Enlarge MAX_CPUS to 512 = 128*2*2 with 2 socket configuration considered. Change-Id: I8dc46dcdd3ca1c3ddfa47fbb28912a2c6e4c46fa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84312 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZEGang Chen
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR, this default size is enough. Use the default size so that more CAR spaces could be saved for other purpose. Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-13soc/intel/ptl: Do initial Panther Lake SoC commit till ramstageSaurabh Mishra
List of changes: 1. Add required SoC programming till ramstage. 2. Include only required headers into include/soc. 3. Skeleton code used to call FSP-S API. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-13soc/intel/cmn/block/cpu: Simplify calculation of non-eviction waysSubrata Banik
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient. This achieves the same ceiling operation but with potentially improved efficiency (less instructions). No functional changes are expected. TEST=Able to build and boot google/rex. Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-12soc/mediatek: Remove redundant struct pad_func and PAD_* definitionsYidi Lin
Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch also refactors the PAD_* macros by, - Repurposing PAD_FUNC and dropping PAD_FUNC_SEL. - Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit initialization. BUG=none TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11soc/intel/raptorlake: Fall back to Intel microcode repoFelix Singer
With the release 20240910 of the Intel microcode repository, it also includes the updated microcode file with version 0x129, which makes the one from the coreboot blobs repo superfluous. Thus, use the one from the Intel repository again. Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-11soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devicesMaxim Polyakov
These identifiers are not included in the GPU list from Intel [1]. At the same time, 0x9B44 is not PCI DID of graphics device at all: 8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2]. [1] https://web.archive.org/web/20240731152818/https:// dgpu-docs.intel.com/devices/hardware-table.html [2] https://web.archive.org/web/20231004011832/https://devicehunt.com/ view/type/pci/vendor/8086/device/9B44 Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-11tree: Use boolean for dmi_power_optimize_disableElyes Haouas
Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Order Kconfig selectors for FSP pathsNico Huber
Should make the sorting order of the paths more obvious. Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-10intel/alderlake: Drop redundant Client/AlderLake* FSP pathsNico Huber
The Alder Lake "Client" FSP paths have been replaced by symlinks to Raptor Lake in the FSP repo. Hence we get the same files anyway and can spare us to maintain the individual paths. Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-09intel/alderlake: Sort FSP paths, most specific selectors firstNico Huber
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo, we can ignore all the FSP-repo paths. Hence put these first. Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all the "Client" paths then. This makes sure that we don't catch a "Client" by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those). Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-09soc/mediatek/common: Move common GPIO definitions to gpio_defs.hYidi Lin
BUG=none TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-09soc/amd/cezanne: Add an option to enable A/B recovery schemeZheng Bao
Extracted from NDA spec #56995: "The A/B recovery scheme formally separates the SPI flash space into different partitions; a primary, “A” and secondary, “B”, which hold the same set of system firmware. Under this scheme, the partitions A and B can hold identical contents initially, but each partition can be updated individually. Normally the system boots from partition A, but if the A partition is found to be corrupted, the system will switch to partition B and boot. The OEM BIOS can then choose to continue the boot from partition B, or repair partition A using contents from partition B." The Cezanne platform supports both A/B recovery and no recovery method. It needs this flag passed to amdfwtool to enable the A/B recovery layout. Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-09soc/intel/xeon_sp: Reserve MMIO high rangeShuo Liu
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will assign domain MMIO high windows from this range. However, there will be unassigned parts among these high windows for non-domain device usage (e.g. misc devices belonging to an IIO stack but not belonged to any PCIe domains under that stack). This will cause segmentation in MTRR UC coverage. For example, in SPR-XCC where only CPM0/HQM0 are supported and instantiated to PCIe domains, MMIO ranges are still reserved for CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c. Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR calculation, this reservation will connect the discontinued domain MMIO high windows together to form one continuous range, and save MTRR register usage from inadequacy. This change is initially raised for SPR but could be effective for GNR as well. TESTED = Build and boot in intel/archercity CRB, MTRR register usage decreases from 7 to 3 in 2S system. TESTED = Only setting MTRR for below 4GB ranges test fails with LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb) tsc: Detected 2000.000 MHz processor last_pfn = 0x2080000 max_arch_pfn = 0x10000000000 x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM. ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9 ... Call Trace: ? 0xffffffff8f600000 ? setup_arch+0x4bb/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0 ---[ end trace 0e56686fd458f0c5 ]--- update e820 for mtrr modified physical RAM map: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved ... modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved last_pfn = 0x6354e max_arch_pfn = 0x10000000000 Memory KASLR using RDRAND RDTSC... x2apic: enabled by BIOS, switching to x2apic ops Using GB pages for direct mapping ... Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff] DMA zone: 28769 pages in unavailable ranges DMA32 zone: 19122 pages in unavailable ranges BUG: unable to handle page fault for address: ff24b56eba60cff8 BAD Oops: 0000 [#1] SMP NOPTI CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2 ... Call Trace: ? set_pte_vaddr_p4d+0x24/0x35 ? __native_set_fixmap+0x21/0x28 ? map_vsyscall+0x35/0x56 ? setup_arch+0xa00/0xaed ? printk+0x53/0x6a ? start_kernel+0x55/0x507 ? load_ucode_intel_bsp+0x1c/0x4d ? secondary_startup_64_no_verify+0xc2/0xcb CR2: ff24b56eba60cff8 ---[ end trace 0e56686fd458f0c6 ]--- RIP: 0010:fill_pud+0xa/0x62 ... Kernel panic - not syncing: Attempted to kill the idle task! ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-07soc/intel/ptl: Add GPIOs for Panther Lake SOCCliff Huang
Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and defines for ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO ref doc: - PT EDS vol2 - Panther Lake H GPIO Implementation Summary (#817954) BUG=b:348678529 TEST=Verify on Intel Silicon platform for PTL using google/fatcat mainboard. Note that these GPIO changes cannot be verified along as they are merely data structure and defines for the SOC. With the GPIO ASL, we should see the following GPIO instances under /sys/bus/acpi/devices when booting to OS: INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/ Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07soc/intel/{common,alderlake}: Add missing ADL-N SKUsMichał Żygowski
Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-07drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` optionSubrata Banik
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly improves the option's prompt and help text. TEST=Built and booted google/rex successfully. Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-07drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creationSubrata Banik
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling this option can improve boot time on platforms that do not utilize the MBP HOB, such as ChromeOS devices. The option is disabled by default on ChromeOS and enabled by default on other platforms. On ADL-P based platforms, this option is forced to be enabled as ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config from MTL and TGL config file. TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when it is disabled. Also verified that the system boots successfully in both cases. Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-063rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWERMichał Żygowski
Signing is performed with test keys by default, set CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys. Depending on the version of the Talos II firmware this alone might not allow booting because coreboot replaces only part of the stock firmware and its newer versions enable secure boot by default (not to be confused with SecureBoot in EFI). The signing performed in this commit is still a prerequisite and might as well be done on its own. Fixing operation with newer stock firmware will be done in a follow-up change. Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-09-06soc/intel/common/gpio: vm index changes as PTL vm entries are not continuousCliff Huang
Add specific virtual wire mapping structure for: - First pad group does not starts with bit position 0. - vw_index and position are not continuous in between groups within a community. BUG= TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-06soc/mediatek/mt8196: Add EINT supportYidi Lin
Add support to configure GPIOs to pull for external interrupts (EINT). BUG=b:334723688 TEST=Talk with Ti50 TPM using IRQ flow. Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84026 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-06Makefile.mk: compile ECC tools and inject ECC to final imageMichał Żygowski
$ build/cbfstool build/coreboot.rom print FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed) fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed) config 0xa880 raw 1324 LZMA (3308 decompressed) revision 0xae00 raw 726 none build_info 0xb100 raw 122 none (empty) 0xb1c0 null 347108 none header_pointer 0x5fdc0 cbfs header 4 none Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67064 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-09-05soc/intel/pantherlake: Hardcode IOM_BASE_ADDR_MAX valueJeremy Compostella
iasl refuses to perform an arithmetic computation in a QWordMemory parameter and fails with the following error. dsdt.asl 2149: 0x4010800000, ((0x4010800000 + 0x10000) - 1), 0x0, Error 6051 - ^ Address Min is greater than Address Max This commit replaces the arithmetic with the result to define IOM_BASE_ADDR_MAX. BUG=b:348678529 TEST=Build for google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f16 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-05soc/intel/common/systemagent: Fix grammer in commentsYuchi Chen
Change-Id: I62d0e324329fdde599e67efb23f813e3b3c650ef Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84199 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-05soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT tableCliff Huang
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>