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2023-03-01soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeSean Rhodes
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0. Remove the incorrect comment and make the UPD configurable from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-28soc/amd: introduce and use PSTATE_MSR macroFelix Held
Instead of adding the P-state number to the PSTATE_0_MSR number to get the P-state MSR number for the rdmsr call, provide a macro that directly calculates the MSR number for a given power state. Also drop the unused PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs available in the hardware. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-28soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usageFelix Held
The latency values in the _CST package override the values in the p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino, Phoenix and Glinda generate_cpu_entries generates the _CST packages for each CPU device. The coreboot code for Stoneyridge doesn't generate _CST packages for the CPU objects, but those are provided via the PSTATE SSDT binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI tables. The AGESA reference code also sets those two FADT entries to the equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED so this also matches the AGESA behavior. From the ACPI 6.4 spec: "Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT." Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-28soc/amd/stoneyridge/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
IRQ9 is used as ACPI SCI IRQ, so add a define for that and use it in the code like it is also done in the other SoCs in soc/amd. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddb51d70c15ab1d7088f62b61e22510bd1b30b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73320 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso/acpi: use ACPI_SCI_IRQ definitionFelix Held
Since there's a define for the ACPI_SCI_IRQ 9, use the define instead of a magic number in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23c8f62929f3f66192698e10826d10329ef3d8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73319 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/picasso,stoneyridge/acpi: drop unneeded res2 FADT assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the res2 FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa69ae61bea82acf66e7210c4103ef48e36dbdd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73318 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/common/block/apob/apob_cache: use enum cb_errFelix Held
Use enum cb_err to return an error/success state instead of an int in get_nv_rdev and get_nv_rdev_rw. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I73706a93bc1dbc8556e11885faf7f486c468bea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/amd/common/block/apob/apob_cache: include types.hFelix Held
The bool type is used although stdbool.h isn't included. Include types.h which will include both stdint.h and stdbool.h Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5213ddae3ceb36e0b2e09f8ef3f7f414ebdf187f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73316 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28soc/intel/meteorlake: Hook up FSP hyper-threading setting to option APIEran Mitrani
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overridden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Port of commit a182faeb88a0 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API") Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-27soc/amd/stoneyridge/acpi: use available number of CPUs for CPU entriesFelix Held
It's sufficient to generate CPU devices for all available CPU cores/ threads instead of for the maximum number of possible CPU cores/threads. TEST=google/careena with 2 cores still boots and Linux doesn't complain about ACPI errors due to referenced but not present CPU objects. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6850edfa305304060092cb5480f4296f4f5ddacc Reviewed-on: https://review.coreboot.org/c/coreboot/+/73070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/mendocino: Populate type 0x63 entry with right MRC CacheKarthikeyan Ramasubramanian
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the base and size of appropriate MRC cache. Change-Id: I49ec4f64e33c4d5780a7fe6a5540eab42b6cec9f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/common/block/apob_cache: Add support for RECOVERY_MRC_CACHEKarthikeyan Ramasubramanian
If a mainboard has RECOVERY_MRC_CACHE and the recovery mode is enabled, then use APOB data from that section and make any updates to that section. Otherwise continue to use DEFAULT_MRC_CACHE section. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. When in normal mode, DEFAULT_MRC_CACHE is used. Normal Mode Boot1: ------------------ [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x0/0x1e000 [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x0 [INFO ] Updated APOB in flash Normal Mode Boot2: ----------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash When the device is in recovery mode, RECOVERY_MRC_CACHE is used. Recovery Mode Boot1: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [INFO ] APOB RAM hash differs from flash [SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x650000/0x1e000 [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] SF: Successfully erased 122880 bytes @ 0x650000 [INFO ] Updated APOB in flash Recovery Mode Boot2: -------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Recovery Mode to Normal Mode: ----------------------------------------- [DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes) [DEBUG] APOB hash matches flash Switch from Normal Mode to Recovery Mode: ----------------------------------------- [DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes) [DEBUG] APOB hash matches flash Change-Id: I93f357e407c98b6e5fca495f4f779fad54a3430f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/intel/elkhartlake/romstage/fsp_params.c: separate debug paramsMichał Żygowski
This commit separates setting FSP debug params from the rest of code and configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8) are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-27soc/amd/common/fsp/dmi.c: Fill in mem manufacturer from CBIMartin Roth
Because the ChromeOS boards don't fill a manufacturer in for the memory SPDs, that information isn't available from the FSP. We can get the Manufacturer ID based on the memory name from CBI instead. Use this information to fill in an ID so that the manufacturer name is available in the SMBIOS information. BUG=None TEST=Look at dmidecode output Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I810c3191180dd3b566d7ea64006f29b625b10526 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/common/fsp/dmi.c: Add dmi_type16 ECC to memory structMartin Roth
The DMI error correction type was not being filled in, so was reporting as "Error Correction Type: <OUT OF SPEC>". This patch fixes that. Since it's now filling in information for both Type 16 & 17, rename the function to reflect that. BUG=None TEST=dmidecode now reports the type correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6b51612d808c63de1acd2be952cb6c152f8a1be5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-27soc/amd/common/block/simnow: Add SimNow Kconfig optionsFred Reitberger
Add option for mainboards to target builds for SimNow. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id765437b69f1bc3a9f9d7858edcd27e687d5a7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-27tree: Move 'asmlinkage' before type 'void'Elyes Haouas
Move 'asmlinkage' before the function type for consistency. Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-26soc/intel/xeon_sp: Drop unused cpu.h headerArthur Heymans
Change-Id: I42856424d3b55107f1758fb05f7ddbee3550d8b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-25soc/intel/{adl, cmn, mtl}: Refactor MP Init related configsSubrata Banik
This patch optimizes CPU MP Init related configs being used within multiple SoC directory and moving essential configs into common code to let the SoC user to choose as per the requirement. TEST=Able to build and boot google/kano and google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-24Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"Shelley Chen
This reverts commit 363202b43589ec240c4a0c8f5b449fbd5c1333f8. Reason for revert: Seeing some bit flips on the SPI bus, but cannot repro reliably on local builds. Going to downgrade back to 50 MHz to see if builder builds are more stable on each variant as a result. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I4fe76bac915e3b3c794821cd160a66824e38ea83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73214 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/ehl: Select CSE defined ME spec version for elkhartlakeDinesh Gehlot
Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes elkhartlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/cnl: Select CSE defined ME spec version for cannonlakeDinesh Gehlot
Cannonlake based SoCs uses Intel's Management Engine (ME), version 12. This patch selects ME 12 specification defined at common code and removes cannonlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/jsl: Select CSE defined ME spec version for jasperlakeDinesh Gehlot
Jasperlake based SoCs uses Intel's Management Engine (ME), version 13. This patch selects ME 13 specification defined at common code and removes jasperlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Icf4bc651e94d6ec977ed8f2381d7184337dc1ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73139 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/tgl: Select CSE defined ME spec version for tigerlakeDinesh Gehlot
Tigerlake based SoCs uses Intel's Management Engine (ME), version 15. This patch selects ME 15 specification defined at common code and removes tigerlake SoC specific ME code and data structures. BUG=b:260309647 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: If4fbfd7c591794ed945c1e9e8487a9e9723c7551 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73138 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/mtl: Select CSE defined ME spec version for meteorlakeDinesh Gehlot
Meteorlake based SoCs uses Intel's Management Engine (ME), version 18. This patch selects ME 18 specification defined at common code and removes meteorlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I36ee66f94f0c37ab6a134e79e49da9abc83b93cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73137 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-24soc/intel/cmn/block/cse: ME source code at common locationDinesh Gehlot
This patch adds ME specific source code at common location in order to reduce maintenance efforts at SoC level and improve readability. The functionality and code are redundant for various SoC platforms and require more maintenance. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic6622662fd3b8bcc9d9ac8bd6ffa732f5d78801a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73133 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/cmn: Support for ME spec versions for SoCs at common codeDinesh Gehlot
This patch includes ME specification datastructures for various ME versions. Including the ME specification in common code will help current and future SoC platforms to select the correct version based on the applicable configuration. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I83df41d7180d2df419849a0c01c728ff0fe75378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73129 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-24soc/intel/cmn: Include ME specification configuration at commonDinesh Gehlot
This patch includes ME specification configuration for various versions, which will allow SoCs to get ME support by selecting the correct version. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I817d14e52b0d353bbb4316d6362fcb80cbec3cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/73128 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/amd/commmon/gfx: Generalize check for selective GOP initMatt DeVillier
Rather than explicitly checking for Recovery or Developer mode via vboot, use display_init_required() so that vboot is not required, and other instances where the display is needed pre-OS (such as when applying a critical system update) are covered as well. With this change, SoCs implementing selective GOP init will need to select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required() to not assert on compilation. BUG=b:255812886 TEST=build/boot skyrim Change-Id: Iac7e06863764a9f21c8a50fc19050cb5a6627df2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-23soc/amd/mendocino: Generalize check for selective GOP initMatt DeVillier
Rather than explicitly checking for Recovery or Developer mode via vboot, use display_init_required() so that vboot is not required, and other instances where the display is needed pre-OS (such as when applying a critical system update) are covered as well. Select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required() to function properly (and not assert on compilation). BUG=b:255812886 TEST=build/boot skyrim Change-Id: If2fee71bcc11468fd2db0abaafe4ea35e2953993 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-02-23soc/intel/elkhartlake/gpio.c: Fix GPD reset mapMichał Żygowski
The reset bit mapping was incorrectly assigned to GPIO groups. The reset mapping for Community 0 actually reflects the GPD reset mapping. Change the Community 0 reset mapping to the correct default map and fix the GPD reset mapping. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I2b9d093ca7ea0f5087f49671ca457c0b45927918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reservedJonathan Zhang
Change-Id: I5f534a898de4ba58ac7d65c5bd6ee10eafa648e4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23soc/mediatek: Add "DRAM" to Kconfig MEDIATEK_BLOB_FAST_INIT nameYu-Ping Wu
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of "BLOB" is unclear. Add "DRAM" to the name. BUG=b:204226005 TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23Revert "soc/intel/adl: Select CSE defined ME spec version for alderlake"Lean Sheng Tan
This reverts commit 272c9c07bd9c7dcd684614c67487504ce06f7a36. Reason for revert: Sorry was going to give +2 but pressed the submit button and accidentally merged this out of train. Change-Id: I8a2c6407832bdcf3d475209356501f8fc3672f6b Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73213 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-23soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I94cb8a9cbb6167d1a11a012efbd6a135a8692969 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-22soc/amd/picasso,stoneyridge/acpi: drop x_firmware_ctl_[l,h] assignmentFelix Held
The coreboot-common acpi_create_fadt writes a pointer to the FACS table into both firmware_ctrl and x_firmware_ctl_l FADT fields and sets x_firmware_ctl_h to zero. When x_firmware_ctl_[l,h] is non-zero, the pointer in firmware_ctrl will be ignored, but that's what is already done on Cezanne and newer. TEST=Linux doesn't complain about any new ACPI problem on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9eab4dcf828f28a60c6312ec96872aac4cfb266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22soc/amd/picasso,stoneyridge/acpi: drop unneeded ARM_boot_arch assignmentFelix Held
The FADT data structure is zero-initialized in acpi_create_fadt which then calls the SoC-specific acpi_fill_fadt function, therefore it's not needed to assign 0 to the ARM_boot_arch FADT field in acpi_fill_fadt. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica968db1228a2d63e83f2b6c4ea57c5f02bf1504 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73187 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-22soc/intel/xeon_sp/spr: Add common device treeTim Chu
Add common device tree used for EGS platform. Also add register setting shared for all EGS platform. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-22soc/mediatek/mt8188: Fix audio sampling rateJohnson Wang
The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-22soc/mediatek/mt8188: Fix USB2 detection issueShaocheng Wang
MT8188 supports port0/port1 download. The hardware needs a trapping pin to select the port to use. When port1 is selected, the phy of port1 will be switched to port0. That is, port1 connector will be the physical line of port0. Since port0 phy isn't initialized in coreboot, switch back to port1 phy. BUG=b:269059211 TEST=can detect USB2 devices in depthcharge. Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-21soc/amd/phoenix: add VBIOS ID remapping for phoenixRitul Guru
Phoenix2 VBIOS PCI DID is 15c8 though the VBIOS image uses a different PCI ID i.e. 0x1205, so we need to implement map_oprom_vendev for the SoC. Change-Id: I7eef5eb41b781f02abb9dd4098e92a8652a431f5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-20soc/amd/common/include/psp_efs: rename new PSP directory EFS entryFelix Held
The EFS entry at offset 0x14 can point to either the first level PSP directory table or to the PSP combo directory structure that was used before the introduction of the AMD A/B recovery scheme. This scheme is not to be confused with the VBOOT scheme. The PSP verstage code checks if the header this entry points to begins with the PSP_COOKIE, which indicates the entry is a first level PSP directory table. Due to that, the EFS entry at offset 0x14 is always expected to point to a PSP directory table, so rename combo_psp_directory to new_psp_directory to match the actual usage. This EFS entry that points to the PSP directory table is called new_psp_directory, since the entry at EFS offset 0x10 was used on some early AMD chips to point to the older PSP directory table and that one is already called psp_directory. amdfwtool uses the same naming scheme for those two PSP directory table pointers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-20soc/intel/rtd3: Hook up supported states to KconfigSean Rhodes
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it is not, it will break S3 exit. When D3COLD_SUPPORT is not enabled, return `3` (D3Hot). This fixed S3 exit on both TGL and ADL. Tested on StarBook Mk V and Mk VI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-19soc/intel/xeon_sp/finalize.c: Set BIOS_DONE MSR as applicableTim Chu
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP programs certain registers via Notify phase ReadyToBoot and it cannot be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we try to set BIOS_DONE MSR as late as possible to avoid this. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-19soc/intel/common/block/fast_spi: Add SPI Vendor Component LockJonathan Zhang
Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI Vendor Specific Component Capabilities are desired. Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-18soc/intel/meteorlake: Add PM Energy Report feature optionYong Zhi
This patch adds enable/disable FSP DisableEnergyReport feature option to be used in devicetree for power instrument purpose. BUG=None Branch=None Test=Build and boot MTL RVP. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17soc/intel/common/block/graphics: Hook up all ADL-S IGD PCI IDsMichał Żygowski
Some users of MSI Z690-A board reported non-working IGD display during post using various CPUs. As not all PCI IDs were hooked, coreboot didn't detect GOP-provided framebuffer nor passed the framebuffer information to the payload, causing a black screen. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elias Souza <eliascontato@protonmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17soc/intel/common/block/smbus/Kconfig: Drop unused ACPI driver Kconfig symbolElyes Haouas
Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69331 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ART : Active Cooling Relationship Table"Elyes Haouas
Change-Id: Ief8dd9c7f7b82e1cd62de5bc1a361432b0eac4ca Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_ADR: Address" commentElyes Haouas
Change-Id: Ib968fe7f9f95e8f690b46b868fd7d6f9332b4c9a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72664 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_UID: Unique ID" commentElyes Haouas
Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_CID: Compatible ID" commentElyes Haouas
Change-Id: I7db69e2faf412b9c6732f6dfc362d5774094ef27 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17soc/intel/cmn/block/acpi: enable BERT table without crashlogJonathan Zhang
Besides crashlog, there's also other errors such as MCA error, which should be recorded in BERT table. With current code, BERT table is not generated if crashlog is not enabled. Add if statement for SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table when crashlog is not supported. For some server mainboard, crashlog is supported through BMC instead of host firmware. Also check if BERT region is generated when crashlog is not enabled. Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17soc/intel/xeon_sp: move PCH specific code into lbg directoryJonathan Zhang
pmc_lock_smi() and pmc_lockdown_config() have PCH specific implementations. Move them from common lockdown.c and pmc.c into lbg/soc_pmutil.c. Move sata_lockdown_config() and spi_lockdown_config() to lbg/lockdown.c. While here, fix some coding style issues. Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17soc/intel/meteorlake: Improve `incomplete` debug messageSubrata Banik
This patch improves `incomplete` debug messages for missing ACPI name PCI devices. Additionally, using the proper PCI device B:D:F to locate the device with the missing ACPI name. Finally, modify the msg time from Debug to Warning to make it more purposeful. TEST=Able to build and boot google/rex. Without this patch: ``` [DEBUG]  dev->path.devfn=10 [DEBUG]  dev->path.devfn=a2 [DEBUG]  dev->path.devfn=b0 ``` With this patch: ``` [WARN]  Missing ACPI Name for PCI: 00:02.0 [WARN]  Missing ACPI Name for PCI: 00:14.2 [WARN]  Missing ACPI Name for PCI: 00:16.0 ``` Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-17soc/intel/cmn/acpi/pep: Add PCI device number for warning msgSubrata Banik
This patch fixes the wrong warning msg around `Unknown min d_state` with having proper PCI Bus/Device/Function number to help to parse the log better. With this patch: [WARN ]  Unknown min d_state for 20 [WARN ]  Unknown min d_state for 50 [WARN ]  Unknown min d_state for 98 [WARN ]  Unknown min d_state for 9a [WARN ]  Unknown min d_state for f9 With this patch: [WARN ]  Unknown min d_state for PCI: 00:04.0 [WARN ]  Unknown min d_state for PCI: 00:0a.0 [WARN ]  Unknown min d_state for PCI: 00:13.0 [WARN ]  Unknown min d_state for PCI: 00:13.2 [WARN ]  Unknown min d_state for PCI: 00:1f.1 Change-Id: Iccaf26882ce5998469b2be6cf5bc7082f193cb29 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-16soc/intel/elkhartlake/fsp_params.c: wire up remaining ddc paramsMichał Kopeć
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: I434c22cd784e24c76bc47aee8728d28255b762db Reviewed-on: https://review.coreboot.org/c/coreboot/+/72405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-16soc/amd/mendocino/Kconfig: add VGA BIOS ID and file defaultsFelix Held
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Mendocino's Kconfig instead of relying on the board's .config files providing the correct settings. Those settings are per-SoC and not per-board, so this is valid for all boards using the Mendocino APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I09c537d3801123e7ffc01608171918b0396b7a5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16soc/amd/cezanne/Kconfig: add VGA BIOS ID and file defaultsFelix Held
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Cezanne's Kconfig instead of relying on the board's .config files providing the correct settings. Those settings are per-SoC and not per-board, so this is valid for all boards using the Cezanne APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67101d518c6b873ad89932ae39c2deb2ed6a4c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16soc/amd/picasso/Kconfig: update VGA_BIOS_ID's help textFelix Held
map_oprom_vendev_rev is implemented in graphics.c in the SoC directory. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0123cb8ff662445fd0a613711d9e1981272b1235 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-16soc/amd/mendocino: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic96846d74df2dc279e13b22f2a83b6f893954fe8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73009 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/glinda: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I26b96966495dc35a8b4a0cb7d5a841f3812f2a70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73007 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/phoenix: Remove non-functional APCB checkFred Reitberger
The way the PSP_APCB_FILES list is created will always insert at least a space into it. When tested by the if, this space will prevent the else clause from ever running and never generate a build error. Remove the non-functional check. Instead, mainboards should select warn_no_apcb or die_no_apcb to generate a warning message or build error if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib9fe0f05739fb19da2494629dc1d5aaa0ca6431f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73006 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/amd/common: Add die_no_apcbFred Reitberger
Add target to die when no APCB is found. This is not always a fatal case, so mainboards can select between this and warn_no_apcb. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5bbc8dd3200c4781677411e67a4b5f1fe8b20286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-16soc/intel/common/block/pcie/rtd3: Fix root port _ON logicCliff Huang
_ON() calls _STA() at the beginning. If _STA() indicates the device is ON, it exits immediately. The solution is to move this _STA() check into the ONSK logic. In general cases, ONSK remains '0'. NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following by a device reset such as WWAN device. When such device calls its _RST(), it increments OFSK. When the following _OFF() is called, it was scheduled to skip, it will also increments ONSK. Similarly, when the following _ON() is called, it checks if the previous _OFF was skipped or not. If skipped, it needs to do the same. In normal suspend/resume cases, these two variables remains '0'. No _OFF() and _ON() calls are skipped. entire generated code: Method (_ON, 0, Serialized) // _ON_: Power On { If ((ONSK == Zero)) { Local0 = \_SB.PCI0.RP01.RTD3._STA () If ((Local0 == One)) { Return (One) } Acquire (\_SB.PCI0.R3MX, 0xFFFF) EMPG = Zero Local7 = 0x06 While ((Local7 > Zero)) { If ((AMPG == Zero)) { Break } Sleep (0x10) Local7-- } Release (\_SB.PCI0.R3MX) \_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020, 0x00000020, 0x00000020) \_SB.PCI0.STXS (0x015E) If ((NCB7 == One)) { L23R = One Local7 = 0x14 While ((Local7 > Zero)) { If ((L23R == Zero)) { Break } Sleep (0x10) Local7-- } NCB7 = Zero Local7 = 0x08 While ((Local7 > Zero)) { If ((LASX == One)) { Break } Sleep (0x10) Local7-- } } } Else { ONSK-- } } BUG=b:249931687 BUG=b:241850118 TEST=Use above functions and check the generated SSDT table after OS boot. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directoryTim Chu
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. These changes are in accordance with the documentation: * Intel(R) Emmitsburg Platform Controller Hub External Design Specification. Document Number: 606161 * Emmitsburg PCH BIOS Specification. Document Number: 631063. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-16soc/intel/cmn/gfx: Skip warning msg in ChromeOS normal modeSubrata Banik
This patch ensures avoiding displaying wrong warning msg as `Graphics hand-off block not found` during ChromeOS normal mode booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB is expected to be missing.  TEST=Able to build and boot google/rex in normal mode w/o having warning msg.  Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-02-15soc/intel/alderlake: Disable package C-state demotion for Raptor LakeAnil Kumar
While executing S0ix tests on Raptor Lake boards, we observed CPU fails to enter suspend state, causing failure. As a workaround, disable package C-state demotion, till this issue is fixed in ucode. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-15soc/intel/adl: Correct wrongly reported ADL PCH SKULean Sheng Tan
Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs to ADL not RPL, though some RPL SoCs are also using ADL PCH. Hence correct the name reporting to avoid confusion when ADL SoCs were used. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15soc/amd/common: Move missing APCB warning to common areaFred Reitberger
Move missing APCB warning from birman to amd/common so that other mainboards can utilize the same warnings if the APCB is missing. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7ae689726ae4f7ccdf6959e47cbb5aee15cdb690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-15soc/amd/common/Makefile.inc: Extend if case coverageFred Reitberger
Extend the coverage of the 'ifeq ($(CONFIG_SOC_AMD_COMMON),y)' case to the entire file. This matches the coverage of the related Kconfig. Add comments to endif to show which if they are ending. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I369e23e7ee9463ca1ae487d1e2181c760ae1bab2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70208 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-14amdfwtool: use SoC ID info instead of misleading comboable flagZheng Bao
Since it actually depends on the SoC type whether the old PSP directory table pointer or the new comboable PSP directory table pointer is used in EFS, get this information from the SoC ID instead of passing the comboable flag for the SoCs that need to use the new comboable PSP directory table pointer. TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-14soc/intel/alderlake: Add missing SATA DSDT devicePatrick Rudolph
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT. Fixes warning shown in Linux: ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.SATA (20220331/dspkginit-438) Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-14soc/intel/meteorlake: Hook up `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch allows override to the `SkipExtGfxScan` UPD. Ideally a platform with an on-board graphics device should skip scanning external GFX devices aka set this UPD to `1`. BUG=b:228002764 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00e15b71ed67119df9ca6f98a750ede109ff33fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/72947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-13soc/amd/mendocino: Add support for selective GOP driver initMatt DeVillier
Add support for the selective GOP init feature by only running the FSP GOP driver when necessary: if the FMAP cache is invalid, or if the board is booted in either recovery or developer mode. BUG=b:255812886 TEST=tested with rest of patch train Change-Id: I7ddadc254e05aca0fdd7a9567160a9329cb0e15c Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-13soc/amd/common/block/gfx: Use TPM-stored hash for vbios cache validationMatt DeVillier
Write the SHA256 hash of the cached VBIOS data when saving to FMAP, and use it to validate the data read from FMAP on subsequent boots. Add TPM2 as a dependency to the selection of VBIOS_CACHE_IN_FMAP. BUG=b:255812886 TEST=tested with rest of patch train Change-Id: I9c8f23b000b90a1072aeb7a57d3b7b2b2bc626dc Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72402 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/amd/common/Makefile: Only run amdfwread onceFred Reitberger
By saving the results of amdfwread into a file, it only needs to be run once instead of every time amdfwread-offset-size-cmd is called. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I1afaf65b9b2f9fb856aefc3ff37fb3a3442f6369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72924 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/amd/mendocino: Add svc_write_postcode call instead of stubMartin Roth
To assist in debugging, add a way for PSP_verstage to send postcodes to the system. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-13soc/intel/alderlake: Fix ACPI name for DPTFCoolStar
The correct ACPI device for DPTM is TCPU; fixing this puts the participant devices under the correct parent device, and allows Windows to properly go into S0ix. TEST=builb/boot Win11 on google/banshee, verify Si0x functional. Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-13soc/amd/common/block/acpi.ivrs: use SMBUS_DEVFN for FCH IOAPIC device IDFelix Held
Instead of using PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC), use the equivalent SMBUS_DEVFN define. Even though the FCH IOAPIC is in the LPC part of the FCH, it needs the IVRS IOAPIC table's source_dev_id field set to SMBUS_DEVFN which is the function 0 of the FCH PCI device. LPC is function 3 of the FCH device. When assigning LPC_DEVFN to source_dev_id, the kernel from Ubuntu 2022.04 LTS complains about the IOAPIC part of the IVRS table being wrong: AMD-Vi: [Firmware Bug]: : No southbridge IOAPIC found AMD-Vi: Disabling interrupt remapping With SMBUS_DEVFN being used as source_dev_id, no such error is reported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8470d67b2513031e75fb422d4c1c181e017ace0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-02-13soc/amd/phoenix: Expand APOB to 256KFred Reitberger
APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE regions to fit. This requires moving memory addresses around to prevent overlapping memory linker errors. TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds all boards Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-13soc/qualcomm/sc7280: Add support to configure 6bit color depthVinod Polimera
Some of the eDp panels use 6bit color depth as default. Set the default color depth configuration to 6 bit when there is no match with the supported color depths. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72744 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDPVinod Polimera
Correct the interface timing parameter calculation for eDP interface to avoid writing into the blanking region. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I069ca351d8c60d071debb23a5e48840701441977 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72743 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOCJonathan Zhang
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC. In such case, is_pci64bit_alloc() return 1. Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72441 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-11soc/amd/*/Makefile.inc: remove command line soc-nameZheng Bao
The function has already moved to fw.cfg. 4/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Idf9e491ed46ae574ccd17f24925e3e5c595039fa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-11soc/amd/*: Add SOC_NAME in fw.cfg(s)Zheng Bao
2/5 of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: I18f73462a3995038fe93750320dfc053fec969ba Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-10soc/amd(MDN/PHX/Glinda): Update DISABLE_KEYBOARD_RESET_PIN helpMartin Roth
For MDN, PHX, & Glinda platforms, the Keyboard Reset functionality has been moved from GPIO 129 to GPIO 21. Additionally, the issue where the system would reset when the KBDRST_L pin went low even when not configured for Keyboard reset seems to have been fixed, so remove that text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iefe7e00d63777577b59ee98cb974b07afea1fd12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72912 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10soc/amd/common/gfx: add support for VBIOS caching, selective GOP initMatt DeVillier
One of the main functions performed by the FSP GOP driver is to modify the ATOMBIOS tables (part of the VBIOS) in memory based on the display output configuration. This device-specific modified VBIOS can be cached in a FMAP region specific for that purpose, then loaded into memory instead of the "generic" VBIOS, saving the ~130ms execution time of the GOP driver. As this approach only works when no pre-OS display output is needed, limit its use to ChromeOS builds, with the GOP driver enabled, and not booting in either recovery or developer modes. SoCs supporting this feature will need to selectively run the FSP GOP driver as needed, using the same criteria used here to determine whether to load the VBIOS from CBFS or from the FMAP cache. Boards utilizing this feature will need to add a dedicated FMAP region with the appropriate name/size, and select the required Kconfig options. BUG=b:255812886 TEST=tested with rest of patch train Change-Id: Ib9cfd192500d411655a3c8fa436098897428109e Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-02-10soc/intel/common/block/fast_spi: Add SPI BIOS decode lockTim Chu
The SPI BIOS decode lock bit needs to be set, according to Intel EBG EDS dodcumentation. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3366817b42a5878f16575698ebc546fa7852e285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-10soc/intel/{common, meteorlake}: Add support for new MCHSridhar Siricilla
The patch adds support for new Meteor Lake MCH (ID:0x7d16). TEST=Build and boot the system having MCH ID:0x7d16. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-09mb/prodrive/hermes: Hook up wake on USB optionAngel Pons
Hook up the `wake_on_usb` EEPROM setting so that it works as intended. TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3. Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-09src/soc/intel/common/block/pcie/rtd3: Fix root port _STA logicCliff Huang
When enable_gpio is used as active low output, the _STA returns incorrect value. Also, simply the logic for _STA method. When enable pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 0 | | active high | 1 | 1(active) | 1 | | active low | 0 | 1(active) | 1 | | active low | 1 | 0 | 0 | When reset pin is used for _STA: | polarity | tx value| get_tx_gpio() | State | | active high | 0 | 0 | 1 | | active high | 1 | 1(active) | 0 | | active low | 0 | 1(active) | 0 | | active low | 1 | 0 | 1 | Generated _STA method: Ex: for using active low power enable GPIO pin GPPC_H17: Method (_STA, 0, NotSerialized) // _STA: Status { Local0 = \_SB.PCI0.GTXS (0x5C) Local0 ^= One Return (Local0) } TEST=Check the SSDT when booted to OS. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ie6f1e7a5b3e9fd0ea00e1e5b54058a14c6e9e09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72421 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09amdfwtool: Add SOC family definition for CarrizoZheng Bao
For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>