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2024-11-19tree: Remove unused <assert.h>Elyes Haouas
Remove <assert.h> when it is not used. Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-19soc/qualcomm/sc7280/socinfo: Add missing <console/console.h>Elyes Haouas
This to fix Wimplicit-function-declaration error: src/soc/qualcomm/sc7280/socinfo.c:67:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 67 | die("could not match jtagid\n"); | ^ src/soc/qualcomm/sc7280/socinfo.c:81:2: error: call to undeclared function 'die'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 81 | die("could not match jtagid\n"); | ^ Change-Id: If930e39d0c7231975c1a11179fa7dbd9fcc0d1d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85166 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18soc/intel: Assert if `pmc_/gpe0_dwX` values are not uniqueSubrata Banik
This commit adds an assertion to ensure that the values of pmc_/gpe0_dw0, pmc_/gpe0_dw1, and pmc_/gpe0_dw2 in the soc_intel_<soc>_config structure are unique. This check helps to catch potential configuration errors early on, preventing unexpected behavior during system initialization. TEST=Built and booted normally. No assertion failure observed. Able to catch the hidden issue due to overlapping Tier 1 GPE configuration. [DEBUG] CPU: Intel(R) Core(TM) 3 N355 [DEBUG] CPU: ID b06e0, Alderlake-N Platform, ucode: 0000001a [DEBUG] CPU: AES supported, TXT supported, VT supported ... ... [DEBUG] MCH: device id 4617 (rev 00) is Alderlake-N [DEBUG] PCH: device id 5481 (rev 00) is Alderlake-N SKU [DEBUG] IGD: device id 46d3 (rev 00) is Twinlake GT1 [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/pmutil.c', line 163 Change-Id: I6b4f2f90a858b9ec85145bce0542f1ce61d080be Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18soc/intel/pantherlake: Reduce memory test sizeSubrata Banik
Enable upd to reduce size of the memory test. TEST=Able to build and boot google/fatcat. w/o this patch: 951:returning from FspMemoryInit 3,452,595 (365,930) w/ this patch: 951:returning from FspMemoryInit 3,442,823 (353,928) Change-Id: I67f10e234019e260923a28a2d71b83786dcb39ee Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-18soc/intel/pantherlake: Bind SoC config to LowerBasicMemTestSize UPDJeremy Compostella
The lower_basic_mem_test_size SoC setting (LowerBasicMemTestSize UPD) request FSP-M to reduce the size of memory tested after memory training. This option reduces the boot time. This is considered a safe option to enable on a well validated board. BUG=b:357011633 TEST=LowerBasicMemTestSize UPD is set when lower_basic_mem_test_size is set Change-Id: I465e9c138ac8f2079bfd506add4667201a8fa533 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85130 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-17soc/mediatek/common/include/soc/mcu_common: Include <types.h>Elyes Haouas
Include missing <types.h>. Change-Id: I04d18e601e010b64c46f2eb52874d3eb5664b0e1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-16tree: Remove unused <console/console.h>Elyes Haouas
Remove unused include <console/console.h>. Change-Id: I2a7cafd7b755a5c3e2bbfa9fc814bf2686c1ccf1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85163 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp/skx: Load microcodePatrick Rudolph
Update microcode on BSP before MPinit and on all APs if necessary. When the APs already have a MCU loaded, MPinit will skip the update. This aligns the code with other platforms that attempt to update the microcode in MPinit even when FIT already has loaded a MCU. Drop the UPD PcdCpuMicrocodePatchBase to prevent FSP-S from updating MCU before MPinit runs. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I7df6f82055a879a738fd29092e750084557bbd5c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84848 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp/skx: Use Kconfig symbolPatrick Rudolph
Use Kconfig symbol CPU_BCLK_MHZ as done on CPX. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I8a0a51d4280e4370e0e8695f8b9d8f2ed943d9e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-16soc/intel/xeon_sp/skx: Lock PMC in post_mp_initPatrick Rudolph
Since SKX and CPX are using the PCH, copy the code from CPX and lock the PMC in the same place. Reduced code differences between SKX and CPX and will allow to merge the codebase into one. Change-Id: I9495456fc2650b25ba164b336dc10ea0b88989aa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84846 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp: Reduce code differencesPatrick Rudolph
Use get_platform_thread_count() instead of duplicated get_thread_count(), that is also less precise. Change-Id: I70c095c284aab6898b8351e82243f534963f333b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84845 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-16soc/intel/xeon_sp/skx: Lock all PCU registersPatrick Rudolph
Lock all PCU registers on all sockets. The same code can be found on CPX, which is basically the same CPU. Once the differences between CPX and SKX are minimal, the platforms can be merged into one codebase. Change-Id: I73eaa0905e8a418fc9dfe515c42cd257c041cf61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84843 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-14southbridge/intel/common: Improve ACPI _PRT method generationYuchi Chen
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be reused for multiple domains. Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-11-14soc/intel/alderlake: Display early Sign of Life for CSE FW SyncKarthikeyan Ramasubramanian
This will ensure that the user is informed about an ongoing CSE FW Sync. BUG=b:378458829 TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed during CSE FW Sync. Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-14soc/intel/xeon_sp: Reserve PRMRRGang Chen
PRMRR (Protected Region Memory Range Region) are not accessible as normal DRAM regions and needs to be explicitly reserved in memory map. Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-14cpu/x86/mtrr: Use fls/ffs from lib.hShuo Liu
Definitions of __fls/__ffs from lib.h and fms/fls from cpu/x86/mtrr.h are duplicated. Use definition from lib.h which is more generic. Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Suggested-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13soc/intel/alderlake: Use CSE sync in ramstage configSubrata Banik
This patch updates the eSOL rendering logic to use the SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of SOC_INTEL_CSE_LITE_SKU. The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to determine whether to render eSOL during ramstage. The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically indicates whether CSE synchronization is performed during ramstage, making it a more appropriate choice for this purpose. This change ensures that eSOL is rendered correctly during ramstage on platforms that require CSE synchronization. TEST=Able to render eSOL during ramstage for google/trulo. Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-13soc/mediatek/mt8196: Enable lastbus debug hardwareXiwen Shao
Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out on the serial console for bus hanging analysis. TEST=build pass, and check log with: [INFO ] ******************* MT8196 lastbus ****************** [INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 --- [INFO ] 00402504 [INFO ] c34b00d6 [INFO ] 61804050 [INFO ] 00051840 [INFO ] 10401610 BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com> Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-13soc/mediatek/mt8196: Map LPDDR type to mem_chip_typeCrystal Guo
Implement map_to_lpddr_dram_type to convert MT8196 specific DRAM_DRAM_TYPE_T values to mem_chip_type. BUG=b:357743097 TEST=Firmware shows the following log: LPDDR5 chan0(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan0(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank1: density 12288mbits x16, MF 06 rev 0800 Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85099 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-13soc/mediatek: Obtain LPDDR type from trained memory infoCrystal Guo
Add lpddr_type to ddr_base_info struct to obtain LPDDR type from trained memory info. BUG=b:357743097 TEST=build pass Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85033 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-13soc/mediatek/mt8196: Add dram calibration supportJarried Lin
Add support for MT8196 DRAM calibration. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. As MT8196's dramc_param struct size is different from other MediaTek SoCs, replace the hardcoded RW_MRC_CACHE size in common code with a constant derived from chromeos.fmd. The common emi.c can be reused for MT8196 as well, so remove the duplicate mt8196/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. Test=Build pass BUG=b:317009620 Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-12soc/mediatek/**/spi.h: Enclose complex macros in parenthesesYu-Ping Wu
Fix the checkpatch error: Macros with complex values should be enclosed in parentheses Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-12soc/intel/pantherlake: Add config option to limit DRAM frequencySubrata Banik
This patch adds a new config option to limit the maximum DRAM frequency for Pantherlake platforms. The mainboard code should try to set `max_dram_speed_mts` from override device tree if required. BUG=b:373394046 TEST=Able to build and boot google/fatcat. Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101 Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-11-12soc/intel/alderlake: Optimize reset handling for non-UFS bootSubrata Banik
This patch optimizes the reset handling in the Alder Lake romstage while disabling the UFS controller in an uni-boot scenario (a unified AP firmware image can boot both UFS and non-UFS systems). It introduces a check in `mainboard_expects_another_reset()` to skip unnecessary resets when a CSE slot switch is due, meaning CSE is not booting from the RW slot. This saves one reset for non-UFS SKUs when a CSE slot switch is pending. The patch also relocates the `cse_fw_sync()` call after disabling the UFS controllers to ensure the system reset flow can be better optimized and combined with any expected resets due to CSE synchronization. TEST=Able to build google/trulo eMMC sku and able to save one reset. Without this patch: 1. Warm reset after disabling UFS (1st reset) 2. Global reset after CSE sync (2nd reset) 3. Warm reset after disabling UFS (3rd reset) 4. Boot to OS With this patch: 1. Skip disabling UFS if CSE sync is due, aka no reset. 2. Global reset after CSE sync (1st reset) 3. CSE is booting from slot RW meaning CSE sync is done, perform UFS disabling and issue a warm reset after disabling UFS (2nd reset) 4. Boot to OS Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-12soc/intel/cmn/pmc: Perform PM register init for CSESubrata Banik
Before entering FSP-M, AP firmware must ensure the PM1_CNT register reflects the correct sleep state if a global reset occurred. This is crucial when Intel CSE has reset the system, as indicated by the global reset bit and wake status register. If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP firmware must enforce an S5 exit path before handing control to FSP-M for CSE initialization. This ensures proper system initialization and avoids potential issues caused by an inconsistent sleep state. Additionally, clears the PM1 status register (PM1_STS) after retrieving the power state. This prevents stale status information from persisting across power cycles, which could lead to confusion during subsequent boots. BUG=b:265939425 TEST=Verified that `prev_sleep_state` holds the correct value (5 for S5) after CSE performs a global reset. Fixes: Inconsistent sleep state after CSE reset. Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-11soc/intel/{adl, mtl, ptl}: Drop CLFLUSH (X86_CLFLUSH_CAR) configSubrata Banik
This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs (ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type for the RAMTOP range. Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was crucial to ensure data consistency, as WB caches both reads and writes. However, since the RAMTOP range now relies on WC MTRR, the role of CLFLUSH becomes less critical. Removing CLFLUSH in this scenario can improve performance, as it avoids unnecessary cache invalidations. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-11-11soc/intel/common: Apply Intel recommendation for early ramtop cachingSubrata Banik
Configuring the Early Caching Ramtop range as Write-Back (WB) before memory initialization is NOT RECOMMENDED. Speculative execution within this WB range can lead to issues. WB configuration should be applied to this range ONLY AFTER memory initialization is complete. To enable Ramtop caching before memory initialization, use Write-Combining (WC) instead of Write-Back (WB). This change applies the recommendation by always configuring the early ramtop caching range as WC. BUG=b:373290479 TEST=Able to build and boot google/trulo. Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85027 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-11soc/intel/common: Add RAMTOP size in ramtop_tableSubrata Banik
This patch adds a new field, `size`, to the `ramtop_table` structure to store the size of the RAMTOP region. The RAMTOP size is calculated as the difference between the cbmem top and the FSP reserved memory base address, aligned up to the nearest 4MB boundary. This change allows for more accurate tracking of the RAMTOP region and improves compatibility with different memory configurations. Previously, the RAMTOP size was always assumed to be 16MB. This could lead to boot hangs on systems with different memory configurations, where the actual RAMTOP size exceeded 16MB. By dynamically calculating and storing the RAMTOP size, this patch ensures that the correct memory range is used for intermediate caching, preventing boot hangs and improving boot speed. The `update_ramtop()` function is updated to write the calculated RAMTOP size to CMOS along with the RAMTOP address. The `early_ramtop_enable_cache_range()` function is also updated to use the RAMTOP size from CMOS to set the correct MTRR range. BUG=b:373290479 TEST=Built and booted successfully on various platforms. Verified that the RAMTOP size is correctly calculated and stored in CMOS Change-Id: I16d610c5791895b59da57d543c54da6621617912 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-11-11soc/mediatek/common: Increase DEV_MEM memory range to 16GBJarried Lin
Map a proper DRAM range for memory test during calibration. TEST=memory test passed on Rauru BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-11soc/mediatek/mt8196: Increase bootblock size from 70KB to 75KBJarried Lin
Increase the bootblock size to support TPM. TEST=Build pass BUG=b:317009620 Change-Id: I11fb505790a85d967032d48d9aa18e22f525a2e5 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-11soc/intel/pantherlake: Update SAF base addressAnil Kumar
BUG=b:357011633 TEST=build and boot coreboot image on Google/Fatcat board. Change-Id: I14fa8cf06144f46369cc8cab6087c790280e9859 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-10tree: Include static.h for remaining devicetree usagesNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h") and commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that use code generated from the devicetree should directly include static.h. This allows static.h to be removed from device.h, eliminating many unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. Add static.h to the includes of all remaining files that require static devicetree access through config_of_soc(), the sconfig generated names, or DEV_PTR(). Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84591 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-10soc/*: Explicitly include static.h for DEV_PTRNicholas Chin
As per commit 05a13e7ed9b9 ("sconfig: Move (WEAK_)DEV_PTR from device.h to static.h"), sources that require access to devicetree static devices should directly include static.h. This allows static.h to be removed from device.h, eliminating unnecessary dependencies on the devicetree for objects that only need the device types and function declarations. The DEV_PTR macro resolves to names declared in static_devices.h, which is then included in static.h, so include the header whenever the macro is used. Change-Id: Ie281e9a9c015b19bfc96b83021a6e3afd98abcc3 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84677 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-10soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-09arch/x86: Define macros for hard-coded HPET registersYuchi Chen
HPET General Capabilities and ID Register at offset 0x0 and Timer 0 Configuration and Capability Register at offset 0x100 are used to determine the generation of HPET ACPI tables. This patch adds macro definitions for these registers and fields. Definitions are from IA-PC HPET (High Precision Event Timers) Specification Revision 1.0a. Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-09soc/intel/common/block/imc: Add Integrated Memory Controller driverYuchi Chen
Intel common IMC contains an embedded SMBus controller for SPD data access. This patch implements IMC based SPD access supports through MMIO. Register definitons are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Tested-by: Yuchi Chen <yuchi.chen@intel.com> Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-11-09include/spd_bin.h: Add SPD IO layerYuchi Chen
By default, PCH SMBus codes will be called to retrieve SPD data. This patch adds a SPD IO layer so that SoC could implement its specific SPD IO layer functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84201 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-09soc/intel/common/systemagent_server: Add server platform system agentYuchi Chen
Intel server processors have a different system agent design, it has some differences with client platform such as (1) no BDSM and BGSM registers; (2) different alignment size and bit fields in TOLUD, TOUUD and TSEG registers. Thus this patch adds a new common block for server platform system agent. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83318 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/intel/pantherlake: Update power limits configJamie Ryu
This updates power_limits_config for Panther Lake U and H. Source: Intel PTL PDG 813278 Intel PTL FSP Power limit profiles table BUG=b:357011633 TEST=Build fatcat and boot with Panther Lake SoC and RVP. Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2024-11-08device/pci_ids, soc/intel/pantherlake: Add new PTL-H DID0Jamie Ryu
This patch adds new DID0 PCI device IDs for Intel PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list and Panther Lake SoC bootblock to support these new IDs. Source: Intel PTL-FAS. Document Number 812562 BUG=b:347669091 TEST=Build fatcat and boot with Panther Lake SoC with newly added MCH ID. With patch, coreboot log: `[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H` `[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H` Change-Id: I56e795696f661d88828d7549f856eee19c46c942 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2024-11-08soc/mediatek/mt8196: Add SPI driver supportLiya Li
Add SPI controller driver code with support for 8 buses (SPI0 to SPI7). Test=Build pass, verify the wavefroms for SPI0~7 are correct. BUG=b:317009620 Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/mediatek/mt8196: Add PLL and clock init supportGuangjie Song
Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-08soc/intel/xeon_sp: Reduce stack usage by 18KiBPatrick Rudolph
Reduce stack usage of acpi_fill_srat_memory() by 18KiB. Directly write the SRAT table entries instead of using a temporary buffer on the stack. FIXES: Crash on ocp/tiogapass when writing SRAT table TEST: Still boots on intel/archercity_crb Change-Id: I91a6787ade8b465da7837b241c0aab00251f7de4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84832 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/intel/common: sata: Opt out in sata_acpi_fill_ssdt() when not namedPatrick Rudolph
When soc_acpi_name() returns NULL do not create the AML code. This prevents errors on the OS side when it tries to parse the AML code and doesn't find a name string for the device: ACPI Warning: Invalid character(s) in name (0x44415F08), repaired: [*_AD] Change-Id: I72225a975663a1028283437cac3b9231b7c77ead Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-08soc/intel/xeon_sp: Create SSDT for Gen6 LPC controllerLu, Pen-ChunX
In coreboot, LPC ACPI objects with its attached devices are usually provided by static DSDT. For Xeon-SP Gen6 LPC, its logical attached devices are created from dynamic SSDT (e.g. super IO). Create a simple SSDT for LPC in dynamic way as well to complete the device relationship chain. Fix below issues during Linux OS boot. The issue will block Windows OS boot as well. [ 22.986142] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.DI00.LPCB], AE_NOT_FOUND (20230628/dswload2-162) [ 22.986792] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) [ 22.987786] ACPI: Skipping parse of AML opcode: Scope (0x0010) Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84842 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-08soc/intel/xeon_sp/gnr: Enable IRQ routingShuo Liu
Enable IRQ routing per PCH IRQ usage convention and report domain _PRT. Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84328 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/intel/[tiger|cannon|meteor]lake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/meteorlake/fsp_params.c: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild for GOOGLE_HATCH, GOOGLE_VOLTEER, GOOGLE_KARIS Change-Id: I169b6d3a979c4db78e7c0932a126d8b0a9306da7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85026 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-11-07soc/intel/cmn/block/cse: Add API to check the current boot partitionSubrata Banik
This patch introduces an API to check whether CSE is booting from the RW slot. This information can be used to determine if a CSE firmware update is pending, which would help to optimize the boot flow by knowing if any reset is expected due to CSE sync. TEST=Able to build google/brox. Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for RPL platforms. This patch selects the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is chosen. BUG=b:281846937 TEST=Able to build and boot google/brox and verify MRC version in CBMEM. Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07soc/amd/common/psp/rpmc: bring debug output in line with fmap sectionFelix Held
Call the PSP RPMC NVRAM 'PSP RPMC NVRAM' instead of 'PSP NVRAM' in the debug console output to not be misleading, since the RPMC feature uses the 'PSP_RPMC_NVRAM' fmap section and not the 'PSP_NVRAM' fmap section. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie89dfcfe4b8780f422c222477bb627e03bd3662d Reviewed-on: https://review.coreboot.org/c/coreboot/+/85007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-11-07soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routedLu, Pen-ChunX
acpigen_write_PRT_pre_routed writes _PRT covering all direct subordinate child devices based on interrupt line/pin info from their PCI configuration spaces. It is required that IRQ routing and PCI configuration space update to be done ahead of time. TEST=Build and boot on intel/archercity CRB Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-11-07soc/mediatek/common: Use write32p and read32p for trackerYidi Lin
TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84959 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/mediatek/common: Refactor `struct tracker`Yidi Lin
Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-06soc/intel/alderlake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/alderlake/fsp_params.c:936:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84939 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/alderlake: select UDK_202305_BINDING for RPLRonak Kanabar
RPL FSP v5311 uses 202305 Edk2. Select UDK_202305_BINDING Kconfig for RPL SoC. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84722 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-06soc/intel/jasperlake: add support for RP LTR mechanismLawrence Chang
Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Ruth <druth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/screebo with single and dual displays, no redundant boot splash. Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81034 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/mediatek/mt8196: Disable irq2axi featureRunyang Chen
Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/mediatek/mt8196: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 58ms in bootblock. (78ms -> 20m) BUG=b:361729697 TEST=check cbmem Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84897 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/rauru: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. BUG=b:361728592 TEST=The boot time improves 62ms Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-05soc/amd/common/psp_smi_flash: refactor SPI controller busy checkFelix Held
Since the functions that call 'spi_controller_available' end up checking if the SPI controller is busy, refactor the function into 'spi_controller_busy' to simplify the logic on the caller's side. Also move printing of the notice that the SPI controller is busy to 'spi_controller_busy' to not have that duplicated in caller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84920 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/amd/common/psp_smi_flash: factor out get_flash_deviceFelix Held
Since the RPMC-related functions will only need the spi_flash struct, but not the region_device struct of the store region corresponding to the 'target_nv_id', factor out 'get_flash_device' from 'find_psp_spi_flash_device_region'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84905 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ana Carolina Cabral
2024-11-05soc/intel/alderlake: Disable UFS controllers only on S5 resumeSubrata Banik
Disable UFS controllers during romstage initialization only when resuming from S5 (full power off). On warm reboot, the UFS controllers are already disabled by the previous boot cycle, so disabling them again is unnecessary. TEST=Able to ensure UFS controller is already disabled in warm reboot path and not causing any problem during S0ix cycle test. Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-05soc/intel/meteorlake: Disable eSOL for Ovis/DekuSubrata Banik
Disable the `FSP_UGOP_EARLY_SIGN_OF_LIFE` option (eSOL) for the Ovis baseboard. eSOL currently only supports display output over eDP and HDMI. Ovis/Deku exclusively use Type-C for display, and eSOL cannot render output over Type-C during early boot because it depends on Type-C firmware loaded in a later stage. TEST=Able to build and boot google/deku. Change-Id: I5ddbd340f667b1631a42d130a793f0b1831aa0ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-11-04soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcsYu-Ping Wu
The size of the inner array of the 2-dimensional array pad_funcs should be 4 instead of SPI_BUS_NUMBER (6). This bug leads to two extra gpio_set_mode() calls with unexpected GPIOs. Inspecting spi.o, the data immediately after the .rodata.pad_funcs section is .rodata.spi_ctrlr_bus_map, with the following data: 00000428 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00000438 00 00 00 00 00 00 00 00 ... This is equivalent to the following calls: gpio_set_mode(GPIO(GPIO05), 0); gpio_set_mode(GPIO(GPIO00), 0); The second call is already included in the pad_funcs array, so the first call is the only practical impact of this bug. Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-03soc/intel/alderlake: Do lazy reset after disabling UFSKarthikeyan Ramasubramanian
If the mainboard expects upcoming reset, then skip the reset after disabling UFS. This will reduce the number of resets during firmware update. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and confirm that the number of reset is reduced by 2 resets. Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-30soc/intel/pantherlake: Populate and pass DRAM info for SMBIOSSubrata Banik
This patch implements the `save_dimm_info()` API to populate and pass DRAM-related information to the next stage. This information is used to generate the SMBIOS memory table, providing details about installed DIMMs. This addresses the issue where SMBIOS lacked detailed DIMM information. Verified that `dmidecode` correctly dumps the DIMM information from the SMBIOS table after this change. BUG=b:376103463 TEST=Built and booted successfully. Verified DIMM info in SMBIOS using `dmidecode`. > dmidecode -t 17 ``` Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ... ... Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-3-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-3-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ``` Change-Id: I3b942610272de401589ee0463de9cd0985974774 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-10-30soc/intel/pantherlake: Add ACPI names for missing devicesSubrata Banik
This patch adds ACPI names for the following devices: - THC0 (PCI: 00:10.0) - THC1 (PCI: 00:10.1) - SRAM (PCI: 00:14.2) - FSPI (PCI: 00:1f.5) TEST=Able to build and boot google/fatcat without any error. w/o this patch: [ERROR] Missing ACPI Name for PCI: 00:10.0 [ERROR] Missing ACPI Name for PCI: 00:10.1 [ERROR] Missing ACPI Name for PCI: 00:14.2 [ERROR] Missing ACPI Name for PCI: 00:1f.5 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84910 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-30soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0Subrata Banik
This change sets the SMBUS device to min sleep state D0 in the ACPI sleep state table. TEST=Able to build and boot google/fatcat. w/o this patch: [WARN ] Unknown min d_state for PCI: 00:1f.4 w/ this patch: No Error or Warning. Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84909 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-29tree: Fix cast an object of type 'nullptr_t' to 'uintptr_t' errorElyes Haouas
This to fix the error when using C23: cannot cast an object of type 'nullptr_t' to 'uintptr_t' (aka 'unsigned long') return (uintptr_t)NULL; ^ Change-Id: Ibdc8794513a508fc61a5046692f854183c36b781 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-10-28uncore_acpi: Clean up resource codePatrick Rudolph
Use the resource size to determine Vtd BAR size and drop the code to calculate the Vtd BAR size. While on it do not truncate the resource address to 32-bit, since the DMAR entry is 64-bit wide anyway. TEST: Booted on intel/archercity_crb Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Fix iiostack.aslPatrick Rudolph
Align DSDT names with SSDT naming scheme, as provided by iio_domain_set_acpi_name() and hide unused devices by implementing the _STA method as done on newer platforms. Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Add SAD PCI driverPatrick Rudolph
Get rid of some helper functions by properly using a pci_driver. Configure SAD if necessary and lock SAD if necessary in the newly added SAD PCI driver. This allows to drop lock_pam0123(), unlock_pam_regions() and socket0_get_ubox_busno(). - Fixes SAD instance on secondary sockets not decoding the C-F segments as DRAM, which would prevent those sockets to access the ACPI/SMBIOS table anchor - Adds PCI multi segment support (SKX and CPX only, other were working properly already) - Moves locking of PAM0123_CSR and PAM456_CSR from SoC to driver code Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84794 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/amd/common/psp: add RPMC provisioning codeFelix Held
Add the code to request the provisioning of the RPMC root key from the PSP. When RPMC hasn't already been provisioned enabled and the PSP has detected a SPI flash chip that both supports RPMC and has monotonic counters that can still be provisioned, we send the PSP mailbox command to request the RPMC provisioning and then reset the system, so the PSP can do the actual provisioning. TEST=On an out of tree AMD reference board using the Cezanne SoC code, provisioning RPMC works as expected when selecting the corresponding PERFORM_RPMC_PROVISIONING Kconfig option: 1st boot to initiate the RPMC provisioning: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC isn't provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 can still be provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 can still be provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned [DEBUG] RPMC: perform fusing using RPMC counter address 0 [DEBUG] OK [NOTE ] RPMC: Rebooting [INFO ] warm_reset() called! 2nd boot after the provisioning is done: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC is provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 has already been provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 has already been provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7760c0bf7618ca60ef160329d0110ac8109032a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84707 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/amd/common/psp: add code for reporting RPMC statusFelix Held
Add the code to query the status of the replay-protected monotonic counter (RPMC) infrastructure from the PSP and display it in a decoded form. Certain SPI flash chips have 4 32-bit monotonic counters in addition to the actual flash storage. During the RPMC root key provisioning process, which is done at the end of manufacturing, a 256 bit RPMC root key is generated by the PSP and programmed into both SoC fuses and the RPMC SPI flash chip. After that, commands to read or increment the monotonic counters can be sent to the SPI flash which are protected by a HMAC-SHA-256 signature using a key derived from the provisioned RPMC root key. The code to do the RPMC provisioning is added in a follow-up patch. TEST=On an out of tree AMD reference board using the Cezanne SoC code and with the SOC_AMD_COMMON_BLOCK_PSP_RPMC Kconfig option selected, the newly added code prints this on the console after the provisioning was done: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC is provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 has already been provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 has already been provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I498eec58189da710b725ac6575c68ba7ab0bcc43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84706 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/amd/common/block/psp: fix logic bug in psp_get_* functionsFelix Held
The functions psp_get_ftpm_capabilties, psp_get_hsti_state, and psp_get_psp_capabilities which were added in commit 5e7ab1a23346 ("soc/amd/common/psp: add helper functions to retrieve capability bits") have a bug in the 'cmd_status' error handling logic. In case of an error, 'cmd_status' is non-zero, while the check somehow expected the opposite. Fix the bug by returning an error if 'cmd_status' is non-zero. Change-Id: Iafcd185ec4a8a4c0e463b0ac5bac3ef78a0af305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84836 Reviewed-by: Ana Carolina Cabral Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-28soc/mediatek/mt8196: Enable PCIe supportJianjun Wang
Enable PCIe support for mt8196. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I9c0aaa1c6da8c247b319e7ed2317dd871e276461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84698 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/mediatek/mt8196: Add PCIe driver and early init supportJianjun Wang
Add PCIe driver for MT8196 platform. According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met and to save delay time in the ramstage, add an early init data region to store the elapsed time since assertion. This will speed up the boot time by 100ms. PCIe port 1 and port 2 share the same PCIe resources, but PCIe port 2 is not used. Therefore, in mtk_pcie_pre_init(), make sure PCIe port 2 is reset to prevent interference with PCIe port 1. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I826a96822e88972bcd4966b6681797a646adf3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-28soc/mediatek/common: Move PCIe definition to the common directoryJarried Lin
To reduce duplicate pcie.h in other SOC folder, mocw pcie.h to mediatek/common folder TEST=Build pass BUG=b:317009620 Change-Id: I8e29ed4027433700652b07b3461eeb8546d45c9b Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-27soc/intel/skylake/Makefile: Remove dead codeFelix Singer
This code is never reached since the hardware uses different SoCs. Besides, mainboard specific code should not be added to SoC code. Change-Id: Id82d5d0b829442c35c093974c06a029259838a9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-26soc/intel/cmn/fast_spi: Improve debug message for SPI flash windowsSubrata Banik
This commit improves the debug messages when initializing SPI flash windows by adding the window type (Fixed Decode or Extended Decode) to the log output. This makes it easier to understand which window is being initialized and can help with debugging issues related to SPI flash access. w/o this patch: [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 w/ this patch: [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 Change-Id: I904f70f42fa70ea06e6f49bd44631a8491463207 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-24soc/intel/common: Add PCIe device IDs for Snow RidgeYuchi Chen
This patch adds SPI and some accelerator device IDs for SNR platform. IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I7bd135d788816e4c3c42ac937450cf8cdcea00bc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84782 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/broadwell; Use boolean for pch_is_wpt_xxElyes Haouas
Use boolean for pch_is_wpt() and pch_is_wpt_ulx(). Change-Id: Ifd1a46ebdbe08df6cc21ada100b94930b02cd7de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23device/pciexp: Add hot-plug capable helper functionPatrick Rudolph
Add and use a new helper function to determine if a device is 1) a PCIe device 2) it's mark hot-plug capable Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-23soc/intel/xeon_sp: Report PCIe integrated end points under DRHDJincheng Li
In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are used, all PCIe integrated end points should be explicitly listed under the DRHD they are affiliated to. Otherwise, the device MSI setting could fail. TESTED = Build and boot on intel/beechnutcity CRB In CentOS Stream (5.14.0-479.el9.x86_64) 9 5.14.0-479.el9.x86_64, without the changes, below failure logs will occur, [ 6.908347] ------------[ cut here ]------------ [ 6.908353] WARNING: CPU: 0 PID: 8 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908374] Modules linked in: [ 6.908379] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 5.14.0-479.el9.x86_64 #1 [ 6.908385] Hardware name: Intel Beechnut City CRB/Beechnut City CRB, BIOS c1e9362c93be-dirty 09/25/2024 [ 6.908389] Workqueue: events work_for_cpu_fn [ 6.908401] RIP: 0010:pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908411] Code: 90 90 90 0f 1f 44 00 00 48 8b 87 00 03 00 00 89 f2 48 85 c0 74 14 f6 40 28 01 74 0e 48 81 c7 c8 00 00 00 31 f6 e9 19 de ac ff <0f> 0b b8 ed ff ff ff c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 [ 6.908417] RSP: 0000:ffffac47c0137c80 EFLAGS: 00010246 [ 6.908423] RAX: 0000000000000000 RBX: ffff9a0a874e2000 RCX: 000000000000009c [ 6.908428] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff9a0a874e2000 [ 6.908433] RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000001 [ 6.908437] R10: ffff9a0a8adcb258 R11: 0000000000000000 R12: 0000000000000001 [ 6.908440] R13: 0000000000000001 R14: ffff9a0a8738be00 R15: ffff9a0a874e20c8 [ 6.908443] FS: 0000000000000000(0000) GS:ffff9a0ded000000(0000) knlGS:0000000000000000 [ 6.908448] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6.908451] CR2: ffff9a11fffff000 CR3: 00000003cd410001 CR4: 0000000000770ef0 [ 6.908455] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 6.908457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400 [ 6.908460] PKRU: 55555554 [ 6.908462] Call Trace: [ 6.908465] <TASK> [ 6.908470] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908484] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908492] ? msi_capability_init+0x193/0x280 [ 6.908501] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908509] ? __warn+0x7e/0xd0 [ 6.908519] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908527] ? report_bug+0x100/0x140 [ 6.908537] ? handle_bug+0x3c/0x70 [ 6.908545] ? exc_invalid_op+0x14/0x70 [ 6.908551] ? asm_exc_invalid_op+0x16/0x20 [ 6.908561] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908569] msi_capability_init+0x193/0x280 [ 6.908577] __pci_enable_msi_range+0x1a3/0x230 [ 6.908586] pci_alloc_irq_vectors_affinity+0xc3/0x110 [ 6.908594] pcie_port_enable_irq_vec+0x3f/0x250 [ 6.908604] ? __pci_set_master+0x31/0xd0 [ 6.908614] pcie_portdrv_probe+0xdf/0x300 [ 6.908620] local_pci_probe+0x4c/0xa0 [ 6.908627] work_for_cpu_fn+0x13/0x20 [ 6.908635] process_one_work+0x194/0x380 [ 6.908643] worker_thread+0x2fe/0x410 [ 6.908649] ? __pfx_worker_thread+0x10/0x10 [ 6.908655] kthread+0xdd/0x100 [ 6.908665] ? __pfx_kthread+0x10/0x10 [ 6.908673] ret_from_fork+0x29/0x50 [ 6.908686] </TASK> [ 6.908688] ---[ end trace 0000000000000000 ]--- Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84315 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/xeon_sp/ibl: Remove unused logicsJincheng Li
Change-Id: I79b08630753b3aceb94becc8b9d682a3d3ca8310 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84308 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23soc/intel/xeon_sp/ibl: Update registers for reach bootableShuo Liu
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/intel/xeon_sp: Add Kconfig SUPPORT_SIMICS_SIMULATIONShuo Liu
Xeon-SP simics doesn't provide simulation of writable PAM-F (Programmable Attribute Map) segment and hence coreboot needs to enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to EBDA (Extended BIOS Data Area). Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/mediatek/common: Add more definitions for SPMIYidi Lin
The newly added enums and struct members will be used by MT8196. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I32e758cc4244114073606c418a69e0467cdf1039 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/mediatek/common: Maintain common pmif data in pmif_init.cYidi Lin
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move the common pmif data to a separate file in order to reuse common/pmif.c as much as possible. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-10-23soc/mediatek/common: Config CAL_TOL_RATE and CAL_MAX_VAL in SoC folderYidi Lin
MT8196 has differenet configurations from other platforms. Make CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse common/pmif_clk.c BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/pantherlake: Update PlatformDebugOption to Trace ReadyJamie Ryu
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption to Trace Ready to have the safe configurations for Panther Lake ES SoC. This safe configuration will be removed once the feature is fully verified and safe to be set to the default value. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-22soc/intel/alderlake_n: Fix display flicker issue when using internal FIVRSimon Yang
If project set configure_ext_fivr = 0 will cause PchFivrVccstIccMaxControl do not set correctly. BUG=b:361831628 TEST=Verified on Teliks360 that affected DUTs. Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2024-10-21soc/intel: Use NEM+ effective way size for for ADL, MTL and PTLJeremy Compostella
Alder Lake, Meteor Lake and Panther Lake use the effective way size when setting up the Enhanced No-Eviction Mode (cf. `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE'). BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-21soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+Jeremy Compostella
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to consider for NEM+ computation is the effective way size. On Alder Lake, the External Design Specification #627270 "3.5.2 No-Eviction Mode (NEM) Sizes" provides a way to compute the effective way size by reading the number of CBO. Unfortunately, reading the number of CBO is not possible on Meteor Lake and Panther Lake. Therefore, we instead compute the effective way size as the biggest of power of two of the way size which works across all three platforms. The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to control this behavior. The issue addressed by this commit can be observed with the following experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to 0x400000 (4 MB). The number of ways that used to be computed is round(0x400000 / 0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000 NEM+ region. When the bootblock code accesses memory between 3 MB and 4 MB, the core would raise a page fault exception. The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4 ways needs to be mapped to cover the entire 0x400000 NEM+ region. BUG=b:360332771 TEST=Verified on PTL Intel reference platform Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-18soc/xeon_sp: Initially add N-1 IBL codesShuo Liu
N-1 IBL (Integrated Boot Logic) codes are initially forked from EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL codes are a set of stub codes to fulfill build sanity check for GNR SoC and CRB codes before the formal codes are published. Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-16soc/intel/xeon_sp: Allow Memory POR independent of RMTNaresh Solanki
TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs. Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-14soc/intel/*: Add debug prints for misaligned FSP and driver settingsSean Rhodes
Print a warning when the FSP UPD for CNVi Audio Offload is enabled without the corresponding USB ACPI driver being enabled. Throw an error when the USB ACPI driver is enabled without the corresponding UPD being enabled. Change-Id: I449c43998dd379dc68a33db47a2fe51cfe5cda2f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-10-11soc/intel/xeon_sp: Revise IIO domain ACPI name encodingShuo Liu
GNR/SRF supports up to 18 logical IIO stacks. Revise IIO domain ACPI name encoding in below form to support GNR/SRF, prefix (16 bit) | socket (3-bit) | stack (5-bit) Change-Id: I6f4c3c22980f2797dd47c8e0d684e0a3175030b7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-11soc/amd/common/block/psp/Kconfig: drop some 'default n'Felix Held
Since the Kconfig default for boolean options is already 'n', there's no need to add that default to the option. Still kept the 'default n' for the 3 options that result in fuses inside the SoC to be burnt (PERFORM_RPMC_PROVISIONING, PERFORM_SPL_FUSING and PSP_PLATFORM_SECURE_BOOT) to point out the fact that that's not selected by default more clearly. Change-Id: I55971f1f130d8ec23d4572a215008d9465e1520a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 09:42:53 +0000