| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-05-28 | soc/ucb/riscv: Add chip_operations stub | Kyösti Mälkki |
| 2019-12-06 | mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. | Philipp Hug |
| 2018-12-05 | mb/emulation/spike-riscv: Implement mtime_init | Jonathan Neuschäfer |
| 2018-11-05 | riscv: add support smp_pause / smp_resume | Xiang Wang |
| 2018-09-10 | soc/sifive/fu540: Makefile: include mtime_init in ramstage | Philipp Hug |
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang |
| 2015-04-29 | kbuild: automatically include SOCs | Stefan Reinauer |
| 2014-12-01 | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |