coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2018-09-15	soc/sifive: move ram_resource to mainboard	Philipp Hug
2018-09-14	soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation	Philipp Hug
2018-09-14	soc/sifive/fu540: Initialize SDRAM	Philipp Hug
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
2018-09-14	soc/sifive/fu540: create ram_resource with actual memory size	Philipp Hug
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	Philipp Hug
2018-09-13	soc/sifive/fu540: Get SDRAM controller out of reset	Philipp Hug
2018-09-13	soc/sifive/fu540: Update clock settings according SiFive bootloader	Philipp Hug
2018-09-13	uart/sifive: make divisor configurable	Philipp Hug
2018-09-12	soc/sifive/fu540: Initialize PLL and clock	Philipp Hug
2018-09-10	soc/sifive: fix compiler warning	Philipp Hug
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
2018-09-10	soc/sifive/fu540: add CLINT support	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-07-18	sifive/fu540: add empty sdram init and size functions	Philipp Hug
2018-07-17	riscv: add support for modifying compiler options	Xiang Wang
2018-04-26	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer