| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-12-05 | soc/sifive/fu540: Add helper function to get tlclk frequency | Jonathan Neuschäfer |
| 2018-12-04 | soc/sifive/fu540: Load PLL settings from a struct | Jonathan Neuschäfer |
| 2018-12-03 | soc/sifive/fu540: Simplify UART refclk calculation | Jonathan Neuschäfer |
| 2018-09-26 | soc/sifive/fu540: Document #if ENV_ROMSTAGE line | Jonathan Neuschäfer |
| 2018-09-14 | soc/sifive/fu540: Switch clock to 1GHz in romstage | Philipp Hug |
| 2018-09-13 | soc/sifive/fu540: Get SDRAM controller out of reset | Philipp Hug |
| 2018-09-13 | soc/sifive/fu540: Update clock settings according SiFive bootloader | Philipp Hug |
| 2018-09-12 | soc/sifive/fu540: Initialize PLL and clock | Philipp Hug |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |