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2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-30soc/qualcomm: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: If2c2138ed3dc437b924297330805caa8c357853d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14tree; Remove unused <lib.h>Elyes Haouas
Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80433 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24soc/*: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6f502b97864fd7782e514ee2daa902d2081633a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80074 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17tree: More use accessor functions for struct region fieldsNico Huber
Always use the high-level API region_offset() and region_sz() functions. This excludes the internal `region.c` code as well as unit tests. FIT payload support was also skipped, as it seems it never tried to use the API and would need a bigger overhaul. Change-Id: I18f1e37a06783aecde9024c15876b67bfeed70ee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-15soc/qualcomm/{sc7180,sc7280}: Use correct return types for functionsZebreus
Some functions in the headers for sc7180 and sc7280 specified the int as their return type when they should have used enum cb_err. Found while testing GCC 13.2.0 Change-Id: I41331fe708a396f7f2f40359e8ba03c8a46a4d4b Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-04soc/qualcomm/sc7280: Enlarge BOOTBLOCK to 44KYidi Lin
After CB:78800 applied, the bootblock increases 2128 bytes and exceeded its allotted size (40K). Therefore, we enlarge BOOTBLOCK to 44K to solve the compilation error. This patch also increases PRERAM_CBFS_CACHE to 103K to fill the empty space (1K) between TIMESTAMP and TTB. BRANCH=none BUG=none TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: Iae9d44939b29098e823508dd3965a1bae7a69041 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-08-22soc/qualcomm: Add missing newlines for logsYu-Ping Wu
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-24Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"Shelley Chen
This reverts commit 363202b43589ec240c4a0c8f5b449fbd5c1333f8. Reason for revert: Seeing some bit flips on the SPI bus, but cannot repro reliably on local builds. Going to downgrade back to 50 MHz to see if builder builds are more stable on each variant as a result. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I4fe76bac915e3b3c794821cd160a66824e38ea83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73214 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/qualcomm/sc7280: Add support to configure 6bit color depthVinod Polimera
Some of the eDp panels use 6bit color depth as default. Set the default color depth configuration to 6 bit when there is no match with the supported color depths. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72744 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-13soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDPVinod Polimera
Correct the interface timing parameter calculation for eDP interface to avoid writing into the blanking region. BUG=b:255870643 TEST=Validated on sc7280 Zombie development board Change-Id: I069ca351d8c60d071debb23a5e48840701441977 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72743 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08soc/qualcomm/sc7280: init eMMCShelley Chen
Use common sdhci driver in coreboot to initialize eMMC for sc7280. This should allow us to initialize eMMC earlier in the boot process, taking it out of the critical path. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot chromeos-bootimage Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01soc/qualcomm/sc7280: Memlayout change to support new Crypto sha updateVenkat Thogaru
With New Crypto upgrade we need to have 1 block of 4Kb increase in romstage, by which we can see an improvement of Boot performance by 100 msec. BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Boot performance improved by 100 msec observed. Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21treewide: Remove duplicated includesElyes Haouas
<types.h> provides <commonlib/bsd/cb_err.h>, <stdint.h> and <stddef.h>. Change-Id: I966303336e604b1b945df77e5d4c3cccbf045c56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-12-13soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUsSudheer Kumar Amrabadi
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To reduce the binary footprint for chipinfo structure, change its members range from uint32_t to uint16_t. Add helper functions for reading and matching jtagid. Modified socinfo_modem_supported() API to utilize helper functions. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-23src/soc/qualcomm: Remove unnecessary space after castsElyes Haouas
Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69807 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUsShelley Chen
On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. BUG=b:254281839 BRANCH=None TEST=build firmware image and boot and make sure we can boot up Tested on villager, which does not have NVMe and made sure that it boots still. Check cbmem dump to make sure that device configuration entry is still low since it's not initializing PCIe devices: 40:device configuration 730,203 (1,295) Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17Revert "soc/qualcomm/sc7280: Remove NVMe init"Shelley Chen
This reverts commit 1b07797a7b79ea6c11421b61b9cf14b92cb91c66. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10/: Remove "ERROR: "/"WARNING: " prefixes from log messagesElyes Haouas
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07soc/qualcomm/sc7280: Move AOP load and reset handle to RomstageSudheer Kumar Amrabadi
As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-20soc/qualcomm/sc7280: Remove NVMe initShelley Chen
We are required to boot with eMMC enabled in the BIOS to store modem calibration data. Thus, it doesn't make sense to enable NVMe at boot time since we will never boot from NVMe w/o eMMC. We may as well take the boot time reduction (~100ms) by eliminating NVMe initialization. BUG=b:185426670, b:254281839 BRANCH=None TEST=Boot after disabling NVMe and make sure that it still boots Note that we are able to see a little over 100ms in boot time savings with this change. Before: 40:device configuration 824,021 (102,701) After: 40:device configuration 717,402 (44) Cq-Depend: chromium:3964185 Change-Id: I94f614ba0369c073617949285c0781aef5c6263f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-20qualcomm/sc7280: initialize tu struct with zerosVinod Polimera
Coverity is throwing a bunch of "maybe uninitialized" errors for tu struct. Initialize the tu struct with zero. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Change-Id: Ie249ad4f53abc91376445420712364a28618a15a Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-09-12qualcomm/sc7280: remove unnecessary malloc and early return on failureVinod Polimera
Instead of just printing the fatal errors, do early return so that boot up time will be reduced during display init failure. Remove malloc allocation and make tu a local variable. Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-14soc/qualcomm/sc7280: Add SocInfo support in corebootTaniya Das
Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-03qualcomm/sc7280: Add support for edp and mdp driverVinod Polimera
- Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. Panel details: Manufacturer: SHP Model 1523 Serial Number 0 Made week 53 of 2020 EDID version: 1.4 Digital display 8 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 Default (sRGB) color space is primary color space First detailed timing is preferred timing Supports GTF timings within operating range Established timings supported: Standard timings supported: Detailed timings Hex of detail: 5a8780a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 653880a070384d403020350035ae10000018 Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm 0780 07b0 07d0 0820 hborder 0 0438 043b 0440 0485 vborder 0 -hsync -vsync Hex of detail: 000000fd003090a7a7230100000000000000 Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock 350MHz Hex of detail: 000000fc004c513134304d314a5734390a20 Monitor name: LQ140M1JW49 Changes in V2: - Remove Misc delays in edp code. - Move mdss soc code to disp.c - Update EDID read using I2C write & read. Changes in V3: - Remove unrelated delays. - Misc changes. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Monitor name: LQ140M1JW49 Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-08-01soc/qualcomm/sc7280: Enable PCIe driverPrasad Malisetty
Enable PCIe functionality on sc7280 and supply all the needed data for PCIe generic platform driver. BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18soc/qualcomm/sc7280: Support hardware watchdog compilationKshitiz Godara
Add watchdog file compilation and watchdog space memory for sc7280. BUG=b:221393157 TEST=None Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: I6a5c4e55964aa8b4de5a641ca162355591c38fc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-30soc/qualcomm: Do resource transitionKyösti Mälkki
For ipq806x this fixes two resources getting declared with same index. The latter previously overwrote former. Change-Id: Ifee321d930d5433c824e2e977f1bb455766582f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-24sc7180/sc7280: Add missing set_resourcesKshitiz Godara
Added missing set_resources function to avoid error messages in boot up logs. BUG=b:230576402 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Kshitiz Godara <quic_kgodara@quicinc.com> Change-Id: Ie0a5bd345486293ce07e586a423d53740ad377f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-01sc7280: Improve performance by removing delays in cpucp initSudheer Kumar Amrabadi
As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-31soc/qualcomm: Increase SPI frequency to 75 MHzShelley Chen
Increase frequency of sc7280 to 75 MHz. Setting the delay to 1/8 of a cycle as a result of experimentation. BUG=b:190231148 BRANCH=None TEST=Make sure that herobrine board boots HW Engineer measured SPI frequency and verified running at 75 MHz Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I3cf5a7c85f12800a11ece397a354349f2a0a235f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64673 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-31soc/qualcomm: Replace <cbfs.h> with <program_loading.h>Elyes HAOUAS
Change-Id: I0cd9960be80330b0b0bf476213bdc242db647e98 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-02sc7280: Increase SPI frequency to 50 MHzShelley Chen
Based on the datasheet, we can safely increase the SPI frequency of sc7280 to 50 MHz. BUG=b:190231148 BRANCH=None TEST=build and boot BIOS with this config on herobrine boards Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-24soc/qualcomm: Remove unused <timer.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: Ibc08ea20263623159c78b634d34899ac7da0d3c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-14soc/qualcomm/common: Make clock_configure() check for exact matchesShelley Chen
Previously, clock_configure() will configure the clocks to round up to the next highest frequency bin. This seems non-intuitive. Changing the logic to find an exact frequency match and will halt booting if no match is found. Recently fixed a bug in CB:63311, where the clock was being set incorrectly for emmc and was able to find it because of this stricter check. BUG=b:198627043 BRANCH=None TEST=build herobrine image and try to set SPI frequency to number not supported. Ensure device doesn't boot. Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-04-02herobrine: fix emmc and sd card clocksShelley Chen
Found an issue where emmc and sd clocks were being misconfigured due to using incorrect integer values when called instead of the defined enums. Fixing by splitting the clock_configure_sdcc() function into two (sdcc1 and sdcc2) as there was no commonality between the two cases anyway. As a result, we can also get rid of the clk_sdcc enum. BUG=b:198627043 BRANCH=None TEST=build herobrine image and test in conjunction with CB:63289 make sure assert is not thrown. Change-Id: I68f9167499ede057922135623a4b04202f4da9b5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-17qualcomm/sc7280: Add mdp clock support to turbo in corebootTaniya Das
This change supports the configuration and enablement of mdp clock to vote for turbo and supports different display panel resolutions and framerates. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ibf4f11d02b0edf83461dbb7af99fda5f33cd5b71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62371 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17qualcomm/sc7280: Add display external clock support in corebootTaniya Das
Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59611 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28sc7280: Add Modem region to avoid modem cleanup in Secboot rebootT Michael Turney
Modem uses different memory regions based on LTE/WiFi. This adds correct carve-out to prevent region being disturbed. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-28sc7280: enable bl31 and SDI feature supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-01-10src/soc/qualcomm: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Id1e0f4cb9f6181dc2fc45e7b6cb149646111bb3e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-29sc7280: Add support for USBRavi Kumar Bokka
Adding USB addressmap for sc7280. Use common USB driver for sc7280. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-15sc7280: Add CPUCP firmware supportRavi Kumar Bokka
CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-25sc7280: Add AOP FW download supportRavi Kumar Bokka
AOP firmware support from sc7280. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-25soc/qualcomm/sc7280: define the aop symbolsRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I62044f6fcb301c0ca35c42598f998913f9b94b95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-18sc7280: Add GSI FW download supportRavi Kumar Bokka
Add GSI Firmware download support for QUP wrappers. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I68c106c942acadc752351f03843d93612cf9c19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-15soc/qualcomm/sc7280: Enable compression of SHRMShelley Chen
The SHRM region needs to be 4 byte aligned, which make enabling compression slightly more complicated. We need to map it to cached memory before loading it and flushing to memory (in aligned chunks) then remapping the address space back to device memory before beginning execution of the SHRM region. Also, did some cleanup in this file based on comments in CB:49392. BUG=b:182963902 BRANCH=None TEST=Make sure we can still boot to kernel on herobrine Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-07sc7280: Add SHRM firmware supportRavi Kumar Bokka
SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-10-06sc7280: Enable UART driverRajesh Patil
Enable common Uart driver on sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I015e21081391bfe85edf667685bf117401a9ec00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-06sc7280: Enable bootblock compressionRavi Kumar Bokka
This patch enables bootblock compression on SC7280. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Ref link: https://review.coreboot.org/c/coreboot/+/45855 BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-27soc/qualcomm/sc7280: Enable QUP drivers to use lz4 compressionShelley Chen
BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-21sc7280: Enable SPI driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21sc7280: Enable I2C driverRajesh Patil
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-21sc7280: Refactor QUP driverRajesh Patil
Enable common qup driver in sc7280 BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: I0e9049557ff63898037210e72333e1739ab62413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-16mainboard/google: Update the TLMM registers for sdhcShaik Sajida Bhanu
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16soc/qualcomm: clock: Clean up clock driverTaniya Das
Updated return type as CB_SUCCESS and aligned indentation. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03sc7280: Refactor QSPI driverRoja Rani Yarubandi
Refactor Qcom QSPI driver to separate common and SoC specific driver code. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Rajesh Patil <rajpat@codeaurora.org> Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03soc/qualcomm/sc7280: DDR One-Time-Training SupportRavi Kumar Bokka
Introduce DDR One-Time-Training Support Device reboots without training from second iteration and also DDR training data is 32kb size, hence update required in memlayout and to sync with upstream changes the Fmap size even got bumped up. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I81038c5c7802c154f4310509c6c64710580b8ce4 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-09-03qualcomm/sc7280: Move to use common clock driver for sc7280Taniya Das
It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. Also add support for Zonda PLL enable for CPU in common clock driver. Refactor the SC7280 clock driver to use the common clock driver APIs. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-25sc7280: Increased CBFS_MCACHE sizeRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-22soc/qualcomm: move uart_bitbang UART w/gpio code to commonRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/qualcomm/sc7280: Replace gpio offset value with macroTaniya Das
Use the gpio offset macro instead of a constant value. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-11sc7280: Add target specific GPIO pin definitionsTaniya Das
Add GPIO pin details specific to SC7280 chipset for the consumers to be able to request for the gpio functionality as per their requirement. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas@codeaurora.org> Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-04sc7280: Reserve wlan & wpss dram regions index order correctedRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: Reserve wlan & wpss dram memory regionsRavi Kumar Bokka
Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: memlayout changes for QCSDI & WMM featuresamrab
Change-Id: If5ebcc9a35e0b86321045ef44bb4874144c6402f Signed-off-by: Sudheer Kumar Amrabadi <samrab@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-05-19sc7280: add qclib supportRavi Kumar Bokka
* Qclib_Ver: BOOT.MXF.1.0-00745-KODIAKLC-2 * Chipcode_Release_Tag: r00003.1 Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-21soc/qualcomm/sc7280: Modify Makefile to use sc7280 blobShelley Chen
Now that qc_sec has landed for sc7280 (https://review.coreboot.org/c/qc_blobs/+/51941), we can start using it instead of the sc7180 placeholders. BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I5d1014287238d383ef6cd186888845eba0f69750 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-15sc7280: Provide initial SoC supportRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 13:03:24 +0000