diff options
| author | Yidi Lin <yidilin@chromium.org> | 2023-11-03 16:07:53 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-11-04 17:07:57 +0000 |
| commit | da1a0e891be5f6aed7af703b117a2fe60049f3bc (patch) | |
| tree | 81ae05bf14c800452cc9bd7c9b0cf2c35b0e1584 /src/soc/qualcomm/sc7280 | |
| parent | 2751d2922f7c87a6acf901a0008ac131bf7245db (diff) | |
soc/qualcomm/sc7280: Enlarge BOOTBLOCK to 44K
After CB:78800 applied, the bootblock increases 2128 bytes and exceeded
its allotted size (40K). Therefore, we enlarge BOOTBLOCK to 44K to solve
the compilation error. This patch also increases PRERAM_CBFS_CACHE to
103K to fill the empty space (1K) between TIMESTAMP and TTB.
BRANCH=none
BUG=none
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: Iae9d44939b29098e823508dd3965a1bae7a69041
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7280')
| -rw-r--r-- | src/soc/qualcomm/sc7280/memlayout.ld | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 95824c7aa9..231b9fe653 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -33,12 +33,12 @@ SECTIONS BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 84K, 4K) WATCHDOG_TOMBSTONE(0x14818FFC, 4) - BOOTBLOCK(0x14819000, 40K) - PRERAM_CBFS_CACHE(0x14823000, 102K) - TIMESTAMP(0x1483C800, 1K) - TTB(0x1483D000, 56K) - STACK(0x1484B000, 16K) - VBOOT2_WORK(0x1484F000, 12K) + BOOTBLOCK(0x14819000, 44K) + PRERAM_CBFS_CACHE(0x14824000, 103K) + TIMESTAMP(0x1483DC00, 1K) + TTB(0x1483E000, 56K) + STACK(0x1484C000, 16K) + VBOOT2_WORK(0x14850000, 12K) DMA_COHERENT(0x14853000, 8K) REGION(qclib_serial_log, 0x14857000, 4K, 4K) CBFS_MCACHE(0x14858000,16K) |