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As cpucp prepare takes 300 msec moving to before ramstage
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec
Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Modem uses different memory regions based on LTE/WiFi.
This adds correct carve-out to prevent region being disturbed.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: T Michael Turney <quic_mturney@quicinc.com>
Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Adding USB addressmap for sc7280.
Use common USB driver for sc7280.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ib92b74c8035a8c0148a9aa48e7870b261b832a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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AOP firmware support from sc7280.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ib7027cdf78a9cdcccc8cfff7eef3cc540fb4093e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Add GSI Firmware download support for QUP wrappers.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I68c106c942acadc752351f03843d93612cf9c19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common Uart driver on sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I015e21081391bfe85edf667685bf117401a9ec00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55963
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Ref link: https://review.coreboot.org/c/coreboot/+/45855
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I34a45422e38ea3a47f29e9856fc5679e8aebbcdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I58c2b79ea2feeab0ad4c2b7cdaa041984160a7ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Enable common qup driver in sc7280
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I0e9049557ff63898037210e72333e1739ab62413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Refactor Qcom QSPI driver to separate common
and SoC specific driver code.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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It supports the clock consumers for QUP, SDCC, PCIE, Display to be able
to configure & enable the desired clocks.
The clock driver also supports reset of subsystems like AOP and SHRM.
Also add support for Zonda PLL enable for CPU in common clock driver.
Refactor the SC7280 clock driver to use the common clock driver APIs.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50580
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Ic6c70f917a59e233f6ea518d9c39f73fe84991c3
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47284
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPIO pin details specific to SC7280 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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* Qclib_Ver: BOOT.MXF.1.0-00745-KODIAKLC-2
* Chipcode_Release_Tag: r00003.1
Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16
Signed-off-by: Sudheer Kumar Amrabadi <samrabad@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Now that qc_sec has landed for sc7280
(https://review.coreboot.org/c/qc_blobs/+/51941), we can start using
it instead of the sc7180 placeholders.
BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I5d1014287238d383ef6cd186888845eba0f69750
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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