diff options
author | Ravi Kumar Bokka <rbokka@codeaurora.org> | 2021-03-31 08:04:13 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-15 19:07:26 +0000 |
commit | 0c9eb3153386f9a3e70f3777df7e036a6c6249a3 (patch) | |
tree | 458380f93ab9427c329eaed00299677cf5cc310e /src/soc/qualcomm/sc7280/Makefile.inc | |
parent | d2bb5021fcdd87a668fbfd2c0e1313eebc67a09f (diff) |
sc7280: Provide initial SoC support
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7280/Makefile.inc')
-rw-r--r-- | src/soc/qualcomm/sc7280/Makefile.inc | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc new file mode 100644 index 0000000000..15bc039c30 --- /dev/null +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -0,0 +1,38 @@ +ifeq ($(CONFIG_SOC_QUALCOMM_SC7280),y) + +all-y += ../common/timer.c +all-y += spi.c + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7280/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +SC7280_BLOB := $(top)/3rdparty/qc_blobs/sc7180 + +################################################################################ + +QC_SEC_FILE := $(SC7280_BLOB)/qc_sec/qc_sec.mbn +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.elf + @util/qualcomm/createxbl.py --mbn_version 6 -f $(objcbfs)/bootblock.raw.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin + +endif |