coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-11-23	src/soc/qualcomm: Remove unnecessary space after casts	Elyes Haouas
	Change-Id: Ic6c711fe3fad19c24ca4c01f8d0a4bc002f14bd6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69807 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01	soc/qualcomm/ipq40xx/spi.c: Remove unuseful 'return' in void function	Elyes HAOUAS
	Change-Id: I0ca7cbbf6c4884b58b4ec8a8e3cbc77f118a42f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-10-05	src/soc to src/superio: Fix spelling errors	Martin Roth
	These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
	Commands used: perl -i -p0e 's\|\/\[\s]Permission[\s]to[\s]use,[\s]copy,[\s]modify,[\s]and.or[\s]distribute[\s]this[\s]software[\s]for[\s]any[\s]purpose[\s]with[\s]or[\s]without[\s]fee[\s]is[\s]hereby[\s]granted,[\s]provided[\s]that[\s]the[\s]above[\s]copyright[\s]notice[\s]and[\s]this[\s]permission[\s]notice[\s]appear[\s]in[\s]all[\s]copies.[\s]THE[\s]SOFTWARE[\s]IS[\s]PROVIDED[\s].AS[\s]IS.[\s]AND[\s]THE[\s]AUTHOR[\s]DISCLAIMS[\s]ALL[\s]WARRANTIES[\s]WITH[\s]REGARD[\s]TO[\s]THIS[\s]SOFTWARE[\s]INCLUDING[\s]ALL[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY[\s]AND[\s]FITNESS.[\s]IN[\s]NO[\s]EVENT[\s]SHALL[\s]THE[\s]AUTHOR[\s]BE[\s]LIABLE[\s]FOR[\s]ANY[\s]SPECIAL,[\s]DIRECT,[\s]INDIRECT,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s]OR[\s]ANY[\s]DAMAGES[\s]WHATSOEVER[\s]RESULTING[\s]FROM[\s]LOSS[\s]OF[\s]USE,[\s]DATA[\s]OR[\s]PROFITS,[\s]WHETHER[\s]IN[\s]AN[\s]ACTION[\s]OF[\s]CONTRACT,[\s]NEGLIGENCE[\s]OR[\s]OTHER[\s]TORTIOUS[\s]ACTION,[\s]ARISING[\s]OUT[\s]OF[\s]OR[\s]IN[\s]CONNECTION[\s]WITH[\s]THE[\s]USE[\s]OR[\s]PERFORMANCE[\s]OF[\s]THIS[\s]SOFTWARE.[\s]\\/\|/* SPDX-License-Identifier: ISC /\|s' $(cat filelist) perl -i -p0e 's\|(\#\#)\sPermission[\#\s]to[\#\s]use,[\#\s]copy,[\#\s]modify,[\#\s]and.or[\#\s]distribute[\#\s]this[\#\s]software[\#\s]for[\#\s]any[\#\s]purpose[\#\s]with[\#\s]or[\#\s]without[\#\s]fee[\#\s]is[\#\s]hereby[\#\s]granted,[\#\s]provided[\#\s]that[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice[\#\s]and[\#\s]this[\#\s]permission[\#\s]notice[\#\s]appear[\#\s]in[\#\s]all[\#\s]copies.[\#\s]THE[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED[\#\s].AS[\#\s]IS.[\#\s]AND[\#\s]THE[\#\s]AUTHOR[\#\s]DISCLAIMS[\#\s]ALL[\#\s]WARRANTIES[\#\s]WITH[\#\s]REGARD[\#\s]TO[\#\s]THIS[\#\s]SOFTWARE[\#\s]INCLUDING[\#\s]ALL[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY[\#\s]AND[\#\s]FITNESS.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL[\#\s]THE[\#\s]AUTHOR[\#\s]BE[\#\s]LIABLE[\#\s]FOR[\#\s]ANY[\#\s]SPECIAL,[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s]OR[\#\s]ANY[\#\s]DAMAGES[\#\s]WHATSOEVER[\#\s]RESULTING[\#\s]FROM[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA[\#\s]OR[\#\s]PROFITS,[\#\s]WHETHER[\#\s]IN[\#\s]AN[\#\s]ACTION[\#\s]OF[\#\s]CONTRACT,[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHER[\#\s]TORTIOUS[\#\s]ACTION,[\#\s]ARISING[\#\s]OUT[\#\s]OF[\#\s]OR[\#\s]IN[\#\s]CONNECTION[\#\s]WITH[\#\s]THE[\#\s]USE[\#\s]OR[\#\s]PERFORMANCE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE.\s(\# \n)\|\1 SPDX-License-Identifier: ISC\n\n\|s' $(cat filelist) perl -i -p0e 's\|\/\[\s]Redistribution[\s]and[\s]use[\s]in[\s]source[\s]and[\s]binary[\s]forms,[\s]with[\s]or[\s]without[\s]modification,[\s]are[\s]permitted[\s]provided[\s]that[\s]the[\s]following[\s]conditions[\s]are[\s]met:[\s][1. ]Redistributions[\s]of[\s]source[\s]code[\s]must[\s]retain[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer.[\s][\s][2. ]Redistributions[\s]in[\s]binary[\s]form[\s]must[\s]reproduce[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer[\s]in[\s]the[\s]documentation[\s]and.or[\s]other[\s]materials[\s]provided[\s]with[\s]the[\s]distribution.[\s][3. ].used[\s]to[\s]endorse[\s]or[\s]promote[\s]products[\s]derived[\s]from[\s]this[\s]software[\s]without[\s]specific[\s]prior[\s]written[\s]permission.[\s]THIS[\s]SOFTWARE[\s]IS[\s]PROVIDED.AS[\s]IS.[\s]AND[\s]ANY[\s]EXPRESS[\s]OR[\s]IMPLIED[\s]WARRANTIES,[\s]INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]THE[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY.FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.ARE[\s]DISCLAIMED.[\s]IN[\s]NO[\s]EVENT[\s]SHALL.LIABLE[\s]FOR[\s]ANY[\s]DIRECT,[\s]INDIRECT,[\s]INCIDENTAL,[\s]SPECIAL,[\s]EXEMPLARY,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s].INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]PROCUREMENT[\s]OF[\s]SUBSTITUTE[\s]GOODS[\s]OR[\s]SERVICES;[\s]LOSS[\s]OF[\s]USE,[\s]DATA,[\s]OR[\s]PROFITS;[\s]OR[\s]BUSINESS[\s]INTERRUPTION.[\s]HOWEVER[\s]CAUSED[\s]AND[\s]ON[\s]ANY[\s]THEORY[\s]OF[\s]LIABILITY,[\s]WHETHER[\s]IN[\s]CONTRACT,[\s]STRICT[\s]LIABILITY,[\s]OR[\s]TORT[\s].INCLUDING[\s]NEGLIGENCE[\s]OR[\s]OTHERWISE.[\s]ARISING[\s]IN[\s]ANY[\s]WAY[\s]OUT[\s]OF[\s]THE[\s]USE[\s]OF[\s]THIS[\s]SOFTWARE,[\s]EVEN[\s]IF[\s]ADVISED[\s]OF[\s]THE[\s]POSSIBILITY[\s]OF[\s]SUCH[\s]DAMAGE.[\s]\\/\|/ SPDX-License-Identifier: BSD-3-Clause /\|s' $(cat filelist) $1 perl -i -p0e 's\|(\#\#) Redistribution[\#\s]and[\#\s]use[\#\s]in[\#\s]source[\#\s]and[\#\s]binary[\#\s]forms,[\#\s]with[\#\s]or[\#\s]without[\#\s]modification,[\#\s]are[\#\s]permitted[\#\s]provided[\#\s]that[\#\s]the[\#\s]following[\#\s]conditions[\#\s]are[\#\s]met:[\#\s][1. ]Redistributions[\#\s]of[\#\s]source[\#\s]code[\#\s]must[\#\s]retain[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer.[\#\s][2. ]Redistributions[\#\s]in[\#\s]binary[\#\s]form[\#\s]must[\#\s]reproduce[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer[\#\s]in[\#\s]the[\#\s]documentation[\#\s]and.or[\#\s]other[\#\s]materials[\#\s]provided[\#\s]with[\#\s]the[\#\s]distribution.[\#\s][\#\s][3. ].used[\#\s]to[\#\s]endorse[\#\s]or[\#\s]promote[\#\s]products[\#\s]derived[\#\s]from[\#\s]this[\#\s]software[\#\s]without[\#\s]specific[\#\s]prior[\#\s]written[\#\s]permission.[\#\s]THIS[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED.AS[\#\s]IS.[\#\s]AND[\#\s]ANY[\#\s]EXPRESS[\#\s]OR[\#\s]IMPLIED[\#\s]WARRANTIES,[\#\s]INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]THE[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY.FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.ARE[\#\s]DISCLAIMED.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL.LIABLE[\#\s]FOR[\#\s]ANY[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]INCIDENTAL,[\#\s]SPECIAL,[\#\s]EXEMPLARY,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s].INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]PROCUREMENT[\#\s]OF[\#\s]SUBSTITUTE[\#\s]GOODS[\#\s]OR[\#\s]SERVICES;[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA,[\#\s]OR[\#\s]PROFITS;[\#\s]OR[\#\s]BUSINESS[\#\s]INTERRUPTION.[\#\s]HOWEVER[\#\s]CAUSED[\#\s]AND[\#\s]ON[\#\s]ANY[\#\s]THEORY[\#\s]OF[\#\s]LIABILITY,[\#\s]WHETHER[\#\s]IN[\#\s]CONTRACT,[\#\s]STRICT[\#\s]LIABILITY,[\#\s]OR[\#\s]TORT[\#\s].INCLUDING[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHERWISE.[\#\s]ARISING[\#\s]IN[\#\s]ANY[\#\s]WAY[\#\s]OUT[\#\s]OF[\#\s]THE[\#\s]USE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE,[\#\s]EVEN[\#\s]IF[\#\s]ADVISED[\#\s]OF[\#\s]THE[\#\s]POSSIBILITY[\#\s]OF[\#\s]SUCH[\#\s]DAMAGE.\s(\#* \n)\|\1 SPDX-License-Identifier: BSD-3-Clause\n\n\|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18	soc: Remove copyright notices	Patrick Georgi
	They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-12-19	src/soc/qualcomm: Remove unused <stdlib.h>	Elyes HAOUAS
	Change-Id: I0bb44636f9ce6a9f96f5909926b586d0a6cedd9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37383 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04	Change all clrsetbits_leXX() to clrsetbitsXX()	Julius Werner
	This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/$[cs][le][rt]bits$_le$[136][624]$/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-05-06	Fix code that would trip -Wtype-limits	Julius Werner
	This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-20	src: Use 'include <string.h>' when appropriate	Elyes HAOUAS
	Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
	MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08	src: Use tabs for indentation	Elyes HAOUAS
	Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-23	soc{broadcom,imgtec,mediatek,qualcomm}: stop using spi_xfer_two_vectors	Aaron Durbin
	On a second look broadcom/cygnus and imgtec/pistachio appear to support full duplex. Therefore, remove the use of spi_xfer_two_vectors(). For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such a way that it does not support full duplex. Remove the use of spi_xfer_two_vectors() and explicitly error out when a full duplex transaction is requested. Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25742 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-07	spi: Remove unused/unnecessary spi_init function definitions	Furquan Shaikh
	Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-24	soc/qualcomm/ipq*: Move spi driver to use spi_bus_map	Furquan Shaikh
	This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I6cc8c339e008e16449fa143c1d21e23534bdaf0b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05	drivers/spi: Re-factor spi_crop_chunk	Furquan Shaikh
	spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-02-22	qualcomm/ipq40xx: add vector operation method to SPI	Yuji Sasaki
	Adding spi_xfer_two_vectors as .xfer_vector for ipq40xx spi_ctrlr. Commit c2973d196d1 ("UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING") has added a new driver method xfer_vector to support combined write-read operation within a single CS cycle. The method is wrapped in the spi_xfer_vector() API. When spi_ctrlr structure does not have xfer_vector method, API calls write and read operations sequentially. However the QCA40xx SPI driver has "forced" CS activation-inactivation in xfer method, so individual operation will break CS after write operation, making combined write-read cycle broken. Adding xfer_vector method to spi_ctrlr is a simple fix to prevent this. BUG=None BRANCH=none TEST=built and run on Gale Change-Id: I2258e563d0793bcacd626f78b8e96b3649a8e4a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88a8824951cef4fe293dfa6e3a1a837ae07b6156 Original-Change-Id: I031e85ce5b847353cb1084f6f68b2af8c6f702e1 Original-Signed-off-by: Yuji Sasaki <sasakiy@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/433439 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Reviewed-on: https://review.coreboot.org/18297 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05	spi: Define and use spi_ctrlr structure	Furquan Shaikh
	1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05	spi: Pass pointer to spi_slave structure in spi_setup_slave	Furquan Shaikh
	For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05	spi: Fix parameter types for spi functions	Furquan Shaikh
	1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-22	spi: Clean up SPI flash driver interface	Furquan Shaikh
	RW flag was added to spi_slave structure to get around a requirement on some AMD flash controllers that need to group together all spi volatile operations (write/erase). This rw flag is not a property or attribute of the SPI slave or controller. Thus, instead of saving it in spi_slave structure, clean up the SPI flash driver interface. This allows chipsets/mainboards (that require volatile operations to be grouped) to indicate beginning and end of such grouped operations. New user APIs are added to allow users to perform probe, read, write, erase, volatile group begin and end operations. Callbacks defined in spi_flash structure are expected to be used only by the SPI flash driver. Any chipset that requires grouping of volatile operations can select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and define callbacks for chipset_volatile_group_{begin,end}. spi_claim_bus/spi_release_bus calls have been removed from the SPI flash chip drivers which end up calling do_spi_flash_cmd since it already has required calls for claiming and releasing SPI bus before performing a read/write operation. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17462 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-10	soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C	Varadarajan Narayanan
	Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333314 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9 Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333303 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10	soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support	Varadarajan Narayanan
	Copy 'ipq806x' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4 Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333178 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333293 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie5794c48131ae562861074b406106734541880d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>