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2014-12-17ARM: Use LPAE for Virtual Address TranslationDaisuke Nojiri
This change introduces LPAE for virtual address translation. To enable it, set ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled. TEST=Booted nyan with and without LPAE. Built nyan_big and daisy. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad Original-Reviewed-on: https://chromium-review.googlesource.com/187862 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a Reviewed-on: http://review.coreboot.org/7749 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
The current algo sets dc shift clock divider to 5 and PLLD DIVP to 0, this is causing VCO out of the characterized range for some panels. This CL changes the dc shift clock divider to 1 and calculates a proper DIVP to have the VCO inside the characterized range, i.e., 500MHz ~ 1000MHz. BRANCH=none BUG=none TEST=Verify on below panels the pixel clock frequencies are correct. 1. AUO B133XTN01.3 (69.5 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 69.5 695 12/695/0 with: 69.5 139 3/139/2 2. AUO B140HTT01.0 (141 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: VCO (1410000000) out of range. Cannot support. with: 141 282 2/94/1 3. LG LP140WH8 (76.32 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.32 763.2 5/381/0 with: 76.3125 152.625 8/407/2 4. N116BGE-EA2 (76.42 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.40 764 3/191/0 with: 76.375 152.75 12/611/2 Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195534 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 1b56566786aa86c14f691fa3858b878f27b6b4de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9de93420e60323f143a42db842febdd3706fe44 Reviewed-on: http://review.coreboot.org/7773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched by our PLLD params finding algorithm, after VCO/CF limitations are applied. To support these panels, we want to allow "best matched" params. BRANCH=nyan BUG=none TEST=emerge-nyan_big coreboot chromeos-bootimage; emerge-nyan coreboot chromeos-bootimage; # Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin. Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195327 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c Reviewed-on: http://review.coreboot.org/7771 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have problem showing the text console before graphics interface is initialized, for example "chromeos factory install shim (text only)" or the "splash screen". BRANCH=none BUG=chrome-os-partner:28082 TEST=emerge-nyan coreboot chromeos-bootimage Boots factory install shim and see text console. Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195388 (cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6 Reviewed-on: http://review.coreboot.org/7770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
Dump all SOR registers for debug purpose. By default, this function is not being built in. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76 Original-Reviewed-on: https://chromium-review.googlesource.com/194738 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416 Reviewed-on: http://review.coreboot.org/7769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
This register needs to be set properly during display init. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display works as well. However, the mode setting needs to be based on either devicetree or EDID. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031 Original-Reviewed-on: https://chromium-review.googlesource.com/194739 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c Reviewed-on: http://review.coreboot.org/7767 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: merge a couple of sor setting difference from kernel driverJimmy Zhang
BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still does't work until all related patches are built in. (CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f Original-Reviewed-on: https://chromium-review.googlesource.com/194737 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8 Reviewed-on: http://review.coreboot.org/7766 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Apply sor fix from kernel dc driverJimmy Zhang
Correct SOR attaching sequence. https://chromium-review.googlesource.com/190300 BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still doesn't work until all related patches are built in. (CL:194737 and CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I8aaf65db90e5e45bd9097c9d38b231bd7d41d997 Original-Reviewed-on: https://chromium-review.googlesource.com/194403 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit fea9d288b98dcc6fc32dc93212fa7c4185603646) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6646816809e29c63de65caa7e7146cd3d02902cf Reviewed-on: http://review.coreboot.org/7765 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Initialize display panel by EDID.Hung-Te Lin
Tegra124 family products may want to use many different display panels with various timing settings. To support them, we should initialize display panel by EDID instead of hard-coded values. BUG=none TEST=emerge-nyan coreboot chromeos-bootimage BRANCH=none Original-Change-Id: Ib125a7f9cb1e6c8cf2d79e0baab525acfd1b7a6e Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/192730 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 43ecd473419aa0fbdd22487416b0b6cfea6a20d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6af47db113035e9440e663a769318776c7b6b70b Reviewed-on: http://review.coreboot.org/7764 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-15tegra124: set MOT bit for I2C-over-AUXKen Chang
According to DP version 1.2a, The MOT (Middle-of-Transaction) bit must be set when the I2C transaction does not stop with the current AUX transaction. Thus the correct steps for an I2C read shall be: 1. I2C command write with MOT set to 1 2. I2C command read to the same address with MOT set to 0 BUG=chrome-os-partner:27679 TEST=EDID data read from LP140WH8 panel is correct while it's a repeated pattern of the first 16 bytes without this CL BRANCH=none Original-Change-Id: I0526beffb8852fbbe0eb5bb80e370261617a59b8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194915 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 466ab0e00744f79ae3720474140d95e5f0828de9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic8ad38b4b08989dd7178d59151e1e276b8a58439 Reviewed-on: http://review.coreboot.org/7763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
PLLD, the clock for display, was previously hard-coded to 306MHz. To support more different panels, we should calcualte PLLD by panel pixel clock configuration. Note existing pixel clock configurations for nyan* boards won't work (they used to rely on hard-coded approximated values) so the device trees are also modified. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan_big coreboot chromeos-bootimage See panel correctly initialized and got DEV screen. Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193565 (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916 Reviewed-on: http://review.coreboot.org/7762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Release DMA channel at end of transactionDavid Hendricks
This adds a missing dma_release() at the end of DMA transfers. It probably doesn't matter since we don't do many DMA transfers, though I wouldn't want to hit some corner case with EFS and eventlog. BUG=none BRANCH=none TEST=tested on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I79b30455babe75a13aac827caac88bf7053ec9e4 Original-Reviewed-on: https://chromium-review.googlesource.com/194479 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit dc7dc1d25bd88873b4c1198a6f3723d27c914ddc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8c5da4e104328fd8bce71942e6eda458a37bfe06 Reviewed-on: http://review.coreboot.org/7761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Use correct mask for APB bus widthDavid Hendricks
It worked earlier since the APB and AHB bus widths occupy the same bits in their respective registers. BUG=none BRANCH=none TEST=tested on Nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7 Original-Reviewed-on: https://chromium-review.googlesource.com/194478 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e Reviewed-on: http://review.coreboot.org/7760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
This change takes about 8K of space away from the cbfs cache and repurposes it for the cbmem console buffer. This is a little more than twice the space we currently need for the bootblock and ROM stage to give us some room to grow and for extra debug output if needed. BUG=None TEST=Built and booted on nyan. Checked the cbmem output. BRANCH=None Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193169 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab Reviewed-on: http://review.coreboot.org/7757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: More improvements to the clock initialization macros.Gabe Black
Consolidate the register setting clrsetbits_le32 call to simplify the macros. Add a check for bits of the divisor being dropped. The clock source registers will throw away bits that aren't supported, so we can check for divisor overflow by checking for dropped bits. BUG=None TEST=Purposefully tried to set a clock to a rate which overflows its divisor. Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus frequency was still correct. BRANCH=None Original-Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193348 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9cd79dd974d8a3c31398f8fbd62750b194867891) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id4d8ecfeff52737cdd68999028b37cbdedb0d116 Reviewed-on: http://review.coreboot.org/7738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra: spi: Read the command1 register to ensure the write to it completes.Gabe Black
To ensure that the command1 write which sets the "go" bit completes before other reads to the device. Otherwise, there's a race condition where those register values might still have their values from the last transfer. With different SPI clock frequencies, that could lead to spi_delay being told there were negative bytes still to send. Its expected delay would wrap to a negative value, that was passed to udelay, and the system would sit there for 4 seconds not doing anything. BUG=None TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was causing the 4+ second delay and verified that it no longer happened. BRANCH=None Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193347 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a Reviewed-on: http://review.coreboot.org/7737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: A couple clock fixes.Gabe Black
This fixes two problems with the clock configuration on tegra124. First, the macro which set up the i2c clocks tried to account for the fact that the i2c divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying the target frequency by 2. That doesn't work, unfortunately, because the divisor is actually n + 1, and what n + 1 means depends on where the one's place is in the divisor. Also, when calculating the divisor, the standard C division operator uses truncation to deal any remainder which tends to make the divisor smaller. That has the effect of making the output frequency higher than what was requested. Since it's usually safer to undershoot a frequency than overshoot it, this change makes those divisions round up instead. Finally, the hand tuned temporary UART clock configuration was adjusted so that it still ends up with the same divisor. Without that, very early output from the bootblock is garbled, specifically the coreboot welcome banner, build timestamp, etc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected value. Measured boot time with and without EFS and verified that there was no change. Spot checked the output for errors and verified that none of the bootblock output was garbled. BRANCH=None Had to add the stdlib.h from 89ed6c that hadn't been merged correctly. Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193362 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 164f7010a47d3bbdbc8bb572106140ae186f3807) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I317b66eda929c0e5a5832adca267b8b54c6aae34 Reviewed-on: http://review.coreboot.org/7736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Add tegra_dc_i2c_aux_read to allow reading EDID.Hung-Te Lin
To read EDID, we need to access I2C via DP AUX channel. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan coreboot chromeos-bootimage Original-Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188858 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8f8e98ff5038b57f89332aee75573095c3933dd2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5b1b6ab2940c8265483059fd94a2c4db2a41144a Reviewed-on: http://review.coreboot.org/7735 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
If EFS is enabled and vboot didn't tell us it's going to use the display, we can skip initializing it and save some boot time. BUG=chrome-os-partner:27094 TEST=Built and booted on nyan without EFS in recovery mode and normal mode. Built and booted on nyan with EFS in recovery mode and normal mode. Verified that in normal mode with EFS the display initialization was skipped and boot time was essentially the same as when display initialization was simply commented out. BRANCH=None Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192544 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30 Reviewed-on: http://review.coreboot.org/7734 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
They were only used internal to the SPI drivers and, according to the comment next to their prototypes, were for when the SPI controller doesn't control the chip select line directly and needs some help. BUG=None TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan. BRANCH=None Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192048 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627 Reviewed-on: http://review.coreboot.org/7708 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-18tegra124: remove spurious error messagePatrick Georgi
Configuring a link bandwidth configuration and then complaining that it's invalid seems unreasonable. Change-Id: I6423da6700d4f266222458758c885a4ea47e0df9 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7502 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-18tegra124: actually parse is_lvdsPatrick Georgi
Precedence rules make the compiler optimize const | var ? val1 : val2; into val1. In our case this means not writing 2 << NV_SOR_CSTM_ROTCLK_SHIFT to the register and not caring about the content of is_lvds. Change-Id: I0b02c74f9445f51bfab9eeae2e8eb9480d104708 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7501 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-14tegra124: allow tegra124 devices to run vboot rmoduleAaron Durbin
The non-x86 systems need the monotonic timer interface. Add tegra124's timer implementation so vboot can link. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built nyan with vboot verfication. Original-Change-Id: I75b99b6e07eeab0324495f97472f14a36883161e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190925 (cherry picked from commit 1e632e861f0e6d10cea0010561e410c1d6c2f317) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9ef177f7c7bb90ceacfe25162bb97047a7c8599d Reviewed-on: http://review.coreboot.org/7463 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: i2c: Reset the controller when there's an error.Gabe Black
This is the only way to clear the error bits in the controller. Without clearing them, every future transaction will look like it failed. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with the TPM frequency turned up to 400 KHz. BRANCH=None Original-Change-Id: Ib654e60ec3039ad9f5f96aa7288d3d877e5c843a Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191811 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 7b19a095652f1561590dcca922b9f8c308d7de9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I301b6694cc521601b618973de891e4ed44c6a97d Reviewed-on: http://review.coreboot.org/7460 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: fix the dangerous VPR write orderJoseph Lo
Currently we put the VPR write code just right before the AVP is going to freeze. We have no idea does the write operation successful or not before halting the AVP. And the power_on_main_cpu should be the last step of that. So we make a fix to change the order. BUG=none BRANCH=none TEST=LP0 suspend stress test and check the VPR is correct; LP0 suspend stress test with video playback Original-Change-Id: Ia62dde2a020910de39796d1cf62c1bf185cdb372 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192029 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 51473811fa477cca9ad9cbafdaad4fd4a2309234) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia28329e38fcf12994594b73c805d061804aa01c4 Reviewed-on: http://review.coreboot.org/7459 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14tegra124: Add some functions for resetting peripherals.Gabe Black
These make it possible to reset peripherals without having to dig into the crc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with EFS and with the TPM bus turned up to 400KHz. BRANCH=None Original-Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191810 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 18c6a48623ae6eff70ca05ea15a7901972a7bba3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8f46666bcf51215f332724ea871f14fec2b522f0 Reviewed-on: http://review.coreboot.org/7458 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-11-14t124: Clean up display init functionsJimmy Zhang
The existing display init functions were translated from a script. The new code will play the same functions but are cleaner and readable and easier to be ported to new panel. BUG=none TEST=build nyan and boot up kernel. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8 Original-Reviewed-on: https://chromium-review.googlesource.com/189518 Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 5998f991ea3069d603443b93c2ebdcdcd04af961) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Squashed to pass abuild nyan: Fix the build for big and blaze. The display code for the tegra124 was cleaned up recently, but only the nyan device tree was updated to match the new code, not big's or blaze's. This change copies nyan's device tree over to those other two boards which will get them building again. The settings may not be correct, but they'll be no less correct than they were before. I also updated the copyright date for nyan. BUG=none TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the panel wasn't damaged by the new display code or settings. BRANCH=None Original-Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191364 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ea235f23df31b4ca8006dcdf3628eed096e062b9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icdad74bf2d013c3677e1a3373b8f89fad99f616e Reviewed-on: http://review.coreboot.org/7454 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
This patch changes the ENTRY() macro in asm.h to create a new section for every assembler function, thus providing dcache_clean/invalidate_all and friends with the same --gc-sections goodness that our C functions have. This requires a few minor changes of moving around data (to make sure it ends up in the right section) and changing some libgcc functions (which apparently need to have two names?), but nothing serious. (You may note that some of our assembly functions have data, sometimes even writable, within the same .text section. This has been this way before and I'm not looking to change it for now, although it's not totally clean. Since we don't enforce read-only sections through paging, it doesn't really hurt.) BUG=None TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not output into any binary anymore since no one actually uses it. Original-Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/183891 (cherry picked from commit 4a3f2e45e06cc8592d56c3577f41ff879f10e9cc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieaa4f2ea9d81c5b9e2b36a772ff9610bdf6446f9 Reviewed-on: http://review.coreboot.org/7451 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Add a macro specifically for configuring the I2C controller clocks.Gabe Black
The divider for the I2C clocks works differently than for other IP blocks and needs to be set up to reflect that. There's also a large internal divider which means you have to do extra calculations to determine what the frequency of the bus itself will be based on the I2C controller clock. The new macro takes the desired frequency of the bus itself and figures everything else out. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1 using this function to set up the i2c busses. BRANCH=None Original-Change-Id: Ib62a5659bcc0d0e15de41887514ae8efb8c8129a Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189014 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 24714399a9a89cf33ad20ee43da87e9b04ba394c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a1eabb16fdb27fb813fe6bc56cdcc593eca166e Reviewed-on: http://review.coreboot.org/7417 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Fix some bugs in the clock configuration macros.Gabe Black
There were some missing parenthesis and some extra semicolons which this change adds and removes, respectively. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Verified that the same frequency calculated differently results in the same settings. Before operator precedence would pull apart the frequency calculation and use the pieces in the wrong order. BRANCH=None Original-Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/189013 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 462e61ad898a4d6a99c1d161d77bde245c5b1f5c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifce3aac262cf5e2ec0496c5b3ad894bf6f0f9a46 Reviewed-on: http://review.coreboot.org/7416 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13t124: Skip PLLP init to 408MHzJimmy Zhang
PLLP is configured to 408MHz by hardware on T124. Init PLLP is needed only when to configure it other than 408MHz. BUG=none TEST=build nyan and boot kernel. Original-Change-Id: I8b1abf510ab886e7fddea8864a6d36f12529880e Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188849 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit d32124cb7562cbce1bb929c3e5f238b13a27b752) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I617f77444a8dd97b20763b50066a1298d3b97724 Reviewed-on: http://review.coreboot.org/7415 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13t124: nyan: Enable lock bit on pllJimmy Zhang
A PLL (Phase-Locked Loop) clock must be locked before it is assigned as clock source. Otherwise, this clock is unreliable. Before: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 40009e01, misc(600060e4): 00000000 p base(600060a0): 40002201, misc(600060ac): 00000200 u base(600060c0): 40005001, misc(600060cc): 00000300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 After: c base(60006080): 48003201, misc(6000608c): 03000000 x base(600060e0): 48009e01, misc(600060e4): 00040000 p base(600060a0): 5801980c, misc(600060ac): 00040800 u base(600060c0): 48005001, misc(600060cc): 00400300 d base(600060d0): 48011b0c, misc(600060dc): 40400800 dp base(60006590): 58305a01, misc(60006594): 40000000 BUG=None TEST=build nyan and boot Original-Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188447 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 7e8e2854b2b7d1ed20d74891c3d19b6c3dd41c55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ief9efa6937af26fe1a10a7b360fc2f5477416b97 Reviewed-on: http://review.coreboot.org/7414 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: fix OSC initialization on LP0 resumeAndrew Bresticker
Add a missing "~" so that we mask off just OSC_XOFS field and not the rest of the register. BUG=chrome-os-partner:26326 TEST=XHCI sometimes works after LP0. BRANCH=none Original-Change-Id: I2df2387dbad6920d36aa2ae5e6cd91e9ec42fa08 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188897 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit bdbe9ead46fa883618a4acedd1feaf676e2eb29b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic853e737fc106527eb3bb15c25bf801a36bbff57 Reviewed-on: http://review.coreboot.org/7412 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: fix PLLU parametersAndrew Bresticker
Fix the PLLU parameters to match the recommended values from the TRM, and the values used by the kernel and LP0 blob. This includes adding support for setting an LFCON value. It appears that changing the PLLU parameters across suspend/resume causes XHCI stability issues after resume. BUG=chrome-os-partner:26326 TEST=XHCI works after LP0 suspend/resume on Nyan. BRANCH=none Original-Change-Id: Ia4af12fefeebe607803e7f2f03ee4802367b82c3 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188752 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit bbc8d92eb462e165c2378bcb3055a3a74b47a19b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I687d1709befc2f5dec094ee423f2ff824412996e Reviewed-on: http://review.coreboot.org/7411 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13tegra124: Make the PLLX frequency selectable by model.Gabe Black
The PLLX provides the clock for the main cores which can run at different max frequencies depending on the specific model of Tegra124. This change makes it possible to select a model which will, in turn, select a frequency for PLLX. The default is 2GHz which is the lowest maximum frequency. BUG=chrome-os-partner:25467 TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz. With a change that selects the right model for nyan, verified that the corresponding frequency was selected. BRANCH=None Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1282015048420a518e6c6959ce982be70378211a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923 Reviewed-on: http://review.coreboot.org/7409 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-12tegra124: enable JTAG in Security ModeJimmy Zhang
Once SECURITY_MODE fuse is burned, JTAG is disabled by default. To reenable JTAG, besides chip unique id and SecureJtagControl need to be built into BCT, Jtag enable flag is also needed to be set. BUG=None TEST=Burn SECURITY_MODE fuse, build chip specific BCT, coreboot comes up and jtag hooks up fine. Original-Change-Id: Ic6b61be2c09b15541400f9766d486a4fcef192a8 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186031 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit ff962b81f424c840ef171d4287a65ab79b018a28) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14b496932dbc0ed184a2212a5b33d740e1f34a4e Reviewed-on: http://review.coreboot.org/7403 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
Repurpose config->pwm to mean the particular PWM device (we use PWM1 on nyan), and add code to program the PWM device. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan, regenerate bootimage, and boot. See that the backlight comes up in the bootloader, and brightness can be adjusted via pwm_bl driver in the kernel. Original-Change-Id: I2db047e5ef23c0e8fb66dd05ad6339d60918d493 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185772 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 0dee98dd0c8510ecd630b5c6cb9ea49724dc8b55) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie53610f3afa30b2d8f484685fb0e8c0b12cd8241 Reviewed-on: http://review.coreboot.org/7402 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Fix PWM pinmux functionsAndrew Chew
It seems that someone just stuck the PM3 function for all of the potential PWM pins. Fix this to be more specific to the particular PWM (of which there are four). BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: Ic61a7321fbe28953b22007a1d0b522c3ca8714ad Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185739 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit f19f897fe11a582cc240d98de88c5e2d4dc4e364) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie10173413a5f00e06f5b1803fd93d6cb322cee3d Reviewed-on: http://review.coreboot.org/7399 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Add PWM base addressAndrew Chew
The Tegra PWM base address was missing, so add it. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: Iebf687c6644290e05ee72794cde697658ab6d7cb Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185738 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit b62843f6cfbf870451f658e6df1a3b48256fa4e1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb8578a130d5995345592caa610c57c1d7f28573 Reviewed-on: http://review.coreboot.org/7398 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
We'd been putting some data structures like the framebuffer and the cbmem at the end of memory, but that may not actually be addressable as identity mapped memory. This change clamps the addresses those structures are placed at so they stay below 4GB. BUG=None TEST=Booted on nyan. Went into recovery mode and verified that there was a recovery screen. Forced memory size to be 4GB and verified that the recovery screen still shows up. BRANCH=None Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185571 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615 Reviewed-on: http://review.coreboot.org/7397 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09arm: Thumb ALL the things!Julius Werner
This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). BUG=None TEST=Snow and Nyan still boot. Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182212 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Conflicts: payloads/libpayload/include/arm/arch/asm.h src/arch/arm/Makefile.inc src/arch/arm/armv7/Makefile.inc *** There is an issue with what to do with ramstage-S-ccopts, and *** will need to be covered in additional ARM cleanup patches. Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-22tegra/nyan*: sdram updatesTom Warren
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-16uarts: 32/64 cleanupRonald G. Minnich
We had lots of casts that caused warnings when compiling on RISCV. Clean them up. Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7066 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-22tegra124/nyan: memory and display updatesAndrew Bresticker
tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6914 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-09-22arm: Move libgcc assembly macros to arch/asm.hJulius Werner
libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-22Add check_member macro to allow clean and easy struct offset checkingJulius Werner
This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)
2014-09-17spi: add Kconfig variable for dual-output read enableDavid Hendricks
Add a Kconfig variable so that driver code knows whether or not to use dual-output reads. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5 Reviewed-on: https://chromium-review.googlesource.com/177834 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8) tegra124: implement x2 mode for SPI transfers on CBFS media This implements x2 mode when reading CBFS media over SPI. In theory this effectively doubles our throughput, though the initial results were almost negligibly better. Using a logic analyzer we see a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we want to see further gains here then we'll probably need to tune AHB arbitration and utilization to eliminate bubbles/stalls when copying from APB DMA. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e Reviewed-on: https://chromium-review.googlesource.com/177835 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc) nyan: turn on dual-output reads for SPI flash Nyan's SPI chip is capable of dual-output reads, so let's use it. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df Reviewed-on: https://chromium-review.googlesource.com/177836 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c) Squashed three commits to enable dual output spi reads for nyan. Also fixed the spi_xfer interface that has been updated to use bytes instead of bits. Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6909 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-13arm: Move exception_init() close to console_init()Julius Werner
This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6884 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-09-13tegra124/nyan: display, clock, and other updatesJulius Werner
tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-12tegra124/nyan: various fixes and additionsHung-Te Lin
Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10tegra124: Make tegra124 compilable with serial turned off.Gabe Black
The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10nyan: Use the new pinmux functions as part of UART setup.Gabe Black
The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6861 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-10nvidia-cbootimage: integrate into coreboot makeIsaac Christensen
Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6851 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-09-09arm: Update a stale comment in bootblock .S filesDavid Hendricks
This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6791 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-09tegra124: Switch the bootblock over the ARMv4 impelementation.Gabe Black
The bootblock for the tegra124 runs on the AVP coprocessor which uses the ARMv4 architecture. Switch it over to that architecture. Change-Id: Ie527bbff938e6148c58727d448f9c2e6862da872 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171402 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c1aa76b7607ee40ff848628971a97eea5393aebe) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6784 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-09-08tegra124: return the UART base address based on indexIsaac Christensen
Change-Id: I73a8e56559c7ffdaab39a5c19311221c91565004 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-08ARM: Generalize armv7 as arm.Gabe Black
There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
2014-08-29tegra124: add custom uartGabe Black
tegra124: Add a test function which spams exclamation points on the UART. This function spews characters on the console and, until we have a working console, is an easy way to see whether the system boots to a particular point. For some reason waiting for transmitter to be empty hangs, but transmitting characters still works. Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d) tegra124: Re-enable waiting for the transmitter to empty in the test function. The compiler was emitting code compatible with armv7-a, but the bootblock was running on a core which uses armv4t. By coincidence, it was emitting an instruction which is unavailable on armv4t when checking the value of the UART's LSR register. Now that the bootblock is compiled with more appropriate flags, this code can be re-introduced. Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170997 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d) tegra124: Seperate out the non-UART specific hardcoded init in the bootblock. The hardcoded init in the test function in the bootblock is actually useful generally because it doesn't belong in the UART driver itself but is necessary for the UART to work. Until we have real implementations for the pinmux, etc., we can use that code to get the UART and console going. Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171334 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5) tegra124: Implement and enable serial console support for tegra124. The driver is very similar to the 8250 driver, except it isn't in two parts, and it also spaces its registers 4 bytes apart instead of having them directly adjacent to each other. Also, eliminate the UART test function in the bootblock. It's no longer needed since the actual console output serves the same purpose. Right now the clock divisor is fixed for now, and we'll want to actually figure out what value to use at some point. Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171337 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019) Squashed 4 commits related to uart support for tegra124. Modified the new uart.c to look like the uart.c for exynos5420. Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6764 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-28tegra124: Add a custom bootblock implementation.Gabe Black
This implementation is the same as the general one except that it removes all the things that don't work on an ARMv4. Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171019 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-22ARM: Overhaul the ARM Makefile.Gabe Black
The ARM Makefile was copied from x86 and then modified, and as a result it was carrying a lot of baggage. On top of that, the extra complication made it inflexible, and we need a lot of flexiblity in order to support the fact that the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main CPUs. Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171017 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6709 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-19tegra124: Implement the tegra i2c driver.Gabe Black
This uses the packet mode of the controller since that allows transfering more data at a time. Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172402 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6703 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-19tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.Gabe Black
The pins on tegra are controlled by three different units, the pinmux, the pin group controls, and the GPIO banks. Each of these units controls some aspect of the pins, and they layer together and interact in interesting ways. By default, the GPIOs are configured to pass through the special purpose IO that the pinmux is configured to and so can be ignored unless a GPIO is needed. The pinmux controls which special purpose signal passes through, along with pull ups, downs, and whether the output is tristated. The pingroup controls change the parameters of a group of pins which all have to do with a related function unit. The enum which holds constants related to the pinmux is relatively involved and may not be entirely complete or correct due to slightly inconsistent, incomplete, or missing documentation related to the pinmux. Considerable effort has been made to make it as accurate as possible. It includes a constant which is the index into the pinmux control registers for that pin, what each of the functions supported by that pin are, and which GPIO it corresponds to. The GPIO constant is named after the GPIO and is the pinmux register index for the pin for that GPIO. That way, when you need to turn on a GPIO, you can use that constant along with the pinmux manipulating functions to enable its tristate and pull up/down mode in addition to setting up the GPIO controls. Also, while in general I prefer not to use macros or the preprocessor when writing C code, in this case the set of constants in the enums was too large and cumbersome to manage without them. Since they're being used to construct a table in a straightforward way, hopefully their negative aspects will be minimized. In addition to the low level functions in each driver, the GPIO code also includes some high level functions to set up input or output GPIOs since that will probably be a very common thing to want to do. Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171806 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a) tegra124: Add base address for the pinmux and pingroup registers. There weren't any constants for the pinmux or pingroup registers in the address map header. Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62) Squashed two related commits. Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6702 Tested-by: build bot (Jenkins)
2014-08-19tegra124: Pick addresses to load the rom and ram stages.Gabe Black
If these aren't set, the rom and ram stages will attempt to load at address zero which doesn't work. Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/173540 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 6ac5cea39d423bfcf5bbd53c2cc6228ab89f08b2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6704 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18tegra: Change how tegra124 and tegra include files from each other.Gabe Black
A problem with including the tegra124 directory directly in the include path is that it makes all headers in that directory first level headers available everywhere including places that have nothing to do with the SOC, even headers which were only intended for local use by tegra124 code. This change modifies things a bit to be more like the way the arch headers are chosen. In the tegra124 directory, there's an include directory which has an soc subdirectory in it. That include directory is added to the include path, making it possible to have headers private to the tegra124. When files specific to whatever tegra is being built for are needed, you can include <soc/foo.h> and get the version specific to that particular soc. Also, the soc.h header file was overhauled to use enums instead of defines, to consistently name things as far as their prefix (the less cryptic TEGRA instead of NV_PA) and suffixes like "BASE", and to get rid of values which were specific to U-Boot which we don't need. Since the only thing in the file were address constants, I also renamed the file addressmap.h. It would be included as: <soc/addressmap.h> which I think is easy to remember, does what you'd think it does from the name, and won't conflict with other header files just minding their own business in some other directory. Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172080 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6659 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-15tegra124: fix Kconfig ARCH settingsIsaac Christensen
The initial commit for tegra124 (396b072) was not updated for the new ARCH settings. Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6658 Tested-by: build bot (Jenkins)
2014-08-13Tegra,Tegra124: proposed layout for file hierarchy with exampleRonald G. Minnich
This change shows the source structure for nvidia Tegra and Tegra124 SOC. The problem we are trying to solve is that there is a large amount of common code in the form of .c and .h files across many different Tegra SOCs. The solution is to provide common code in a single directory, but not to compile in the common code directory; rather, we compile in a directory for a given SOC. Different SOCs will sometimes need different bits of code from the common directory. Tegra common code lives in tegra/, but there is no makefile there: if a Tegra common file is needed in a SOC, it is referenced via a Makefile in a specific Tegra SOC. Another issue is includes. Include files in the common directory might be accessed by a piece of code in an SOC directory. More problematically, code in the common directory might require a file in an SOC directory. We don't want to put the SOC name in an #include path, e.g. in a C file in tegra/ is very undesirable, since we might be compiling for a tegra114. On some systems this is solved by a pre-pass which creates a set of symbolic links; on others with nested #ifdef in the common code which include different .h files depending on CPP variables. In previous years, both LinuxBIOS and coreboot have tried these solutions and found them inconvenient and error-prone. We choose to solve it by requiring explicit naming of part of the path of files that are in the common directory. This requirement, coupled with two -I directives in the Makefile.inc, allows common and SOC C code to incorporate both common and SOC .h files. .c and .h files -- SOC or common -- name include files in the common directory with the prefix tegra/, e.g. SOC files will be included from the SOC directory if they have no prefix: The full patch of clock.h will depend on what SOC is being compiled, which is desirable. In this way, a common file can pick up a specific SOC file without creating symlinks or other such tricky magic. We show this usage with one file, soc/nvidia/tega124/clock.c. This compiles. The last question is where to put the prototype for the function defined in this file -- soc.h? Change-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/171569 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 53e3bed868953f3da588ec90661d316a6482e27e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6621 Tested-by: build bot (Jenkins)
2014-08-12tegra124: Implement the monotonic timer by reading the 1us timer register.Gabe Black
It turns out there's a register in tegra which automatically counts at 1us increments. It's primarily intended for hardware to use (I think to drive other timers) but we can read it ourselves since a 1us timer is exactly what we need to support the monotonic timer API. Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172044 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6620 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-12tegra124: Add stack related config options to the Kconfig.Gabe Black
Otherwise the stack ends up down at 0 and has 0 bytes. Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171015 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12tegra124: Add some make rules which will wrap the bootblock in the BCT.Gabe Black
These rules slip into the normal bootblock preperation process and use the cbootimage utility to wrap it in a BCT. Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170924 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-05tegra124: Add a stub implementation of the tegra124 SOC.Gabe Black
Most things still needs to be filled in, but this will allow us to build boards which use this SOC. Change-Id: Ic790685a78193ccb223f4d9355bd3db57812af39 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170836 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 462456fd00164c10c80eff72240226a04445fe60) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6431 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 07:25:41 +0000