summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra124
diff options
context:
space:
mode:
authorHung-Te Lin <hungte@chromium.org>2014-04-18 00:32:41 +0800
committerMarc Jones <marc.jones@se-eng.com>2014-12-16 23:30:52 +0100
commit066b16442956ad9297c40b040b110b92a0dab31d (patch)
treeca2da298c20a120fc1115a4fa4f9efe26d8c2a78 /src/soc/nvidia/tegra124
parent47e3cf8c7feec930388b70558cee45c09d787b77 (diff)
tegra124: Always enable DC when attaching SOR.
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have problem showing the text console before graphics interface is initialized, for example "chromeos factory install shim (text only)" or the "splash screen". BRANCH=none BUG=chrome-os-partner:28082 TEST=emerge-nyan coreboot chromeos-bootimage Boots factory install shim and see text console. Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195388 (cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6 Reviewed-on: http://review.coreboot.org/7770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra124')
-rw-r--r--src/soc/nvidia/tegra124/sor.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index d82020aa31..0e96764b60 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -659,7 +659,8 @@ static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
- /* Enable DC */
+ /* Enable DC now - otherwise pure text console may not show. */
+ WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
WRITEL(reg_val, &disp_ctrl->cmd.state_access);
}