summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra124/clock.c
AgeCommit message (Expand)Author
2015-02-17tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIMEJimmy Zhang
2015-01-04tegra124: configure DP with correct pixel clockVince Hsu
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
2014-12-15tegra124: A couple clock fixes.Gabe Black
2014-11-14tegra124: Add some functions for resetting peripherals.Gabe Black
2014-11-14t124: Clean up display init functionsJimmy Zhang
2014-11-13t124: Skip PLLP init to 408MHzJimmy Zhang
2014-11-13t124: nyan: Enable lock bit on pllJimmy Zhang
2014-11-13tegra124: fix PLLU parametersAndrew Bresticker
2014-11-13tegra124: Make the PLLX frequency selectable by model.Gabe Black
2014-09-22tegra124/nyan: memory and display updatesAndrew Bresticker
2014-09-13tegra124/nyan: display, clock, and other updatesJulius Werner
2014-09-12tegra124/nyan: various fixes and additionsHung-Te Lin
2014-09-11tegra124/nyan: rougly stable code baseGabe Black
2014-08-18tegra: Change how tegra124 and tegra include files from each other.Gabe Black
2014-08-13Tegra,Tegra124: proposed layout for file hierarchy with exampleRonald G. Minnich
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 06:06:35 +0000