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2021-05-05soc/mediatek/mt8195: Add NOR-Flash supportRex-BC Chen
TEST=boot to romstage on MT8195 EVB Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: Add SPI driver supportQii Wang
Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek: Move the common part of SPI drivers to common/Rex-BC Chen
The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-05soc/mediatek/mt8195: add pmif/spmi/pmic driverRex-BC Chen
MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-30soc/mediatek/mt8192: devapc: Add ADSP domain settingTinghan Shen
Configure ADSP domain from 0 to 4 and lock it to prevent changing it unexpectedly. TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Ib938ba05e8d0342572c57366c97ebb0185da8aba Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52728 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/mediatek/mt8195: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin
The PMIC drivers can be shared by MT8192 and MT8195. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add GPIO driverPo Xu
Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add timer supportYidi Lin
TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8192: Remove redundant SPM register definitionYidi Lin
A complete SPM register definition is defined in include/soc/spm.h. Remove the redundant definition from include/soc/pmif_spmi.h. TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: If55e7adabdf32bb4312b910dce9a55621a8da380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/mediatek/mt8195: add register definitionsYidi Lin
Add register definitions for infracfg_ao, topckgen, apmixed and SPM. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie740f22aa12f40950a27a3e0142e2d50a506b251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Initialize watchdogYidi Lin
MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21soc/mediatek: Move mt8192 ufs driver to commonYidi Lin
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I28eb13edcded95a9a4c17bdf92da9f792883a613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-21src/mediatek: Move mt8192 eint driver to commonYidi Lin
The eint driver can be shared by multiple platforms so we want to move it to common/. BRANCH=asurada TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id8e0b631d5079e51213831ed17aa540e0afadd4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-16soc/mediatek: Remove misleading memory logsYu-Ping Wu
When MRC cache region type is not found (for example, in recovery mode with !HAS_RECOVERY_MRC_CACHE), mrc_cache_stash_data() will return 0. Therefore, the platform code is not able to tell from the return value if the MRC cache data is actually written to flash or not. Since the MRC driver is already pretty verbose, ignore the return value and remove the misleading memory logs. BUG=none TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: I6b411664ca91b9be2d4518a09e9734d26db02d6e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52361 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/mediatek: Include sdram_info in ddr_base_infoYu-Ping Wu
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861). BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots with fast calibration BRANCH=asurada Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-13soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin
TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-09mb/google/asurada: select mmc storage configWenbin Mei
Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-09soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei
Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi
We seperate the EoTp packet extra data. So need to reduce the delta. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-27soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_ENDJitao Shi
ANX7625 requires the line packets to end at the same time. Otherwise, the display will be shifted. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Jacuzzi Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-24soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu
Use the MRC cache API for asurada, and sync dramc_param.h with dram blob (CL:*3674585). With this change, the checksum, originally stored in flash, is replaced with a hash in TPM. In addition, in recovery boot, full calibration will always ne performed, and the cached calibration data will be cleared from flash. This change increases ROMSTAGE size from 236K to 264K. Most of the increase is caused by TPM-related functions. Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be moved to soc folder. With this CL, there is no significant change in boot time. Normal AP reboot time (fast calibration) is consistently 0.98s as before, so this change should not affect the result of platform_BootPerf. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots with both full and fast calibration BRANCH=none Cq-Depend: chrome-internal:3674585, chrome-internal:3704751 Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-24soc/mediatek/mt8192: Enlarge ROMSTAGE to 272KYu-Ping Wu
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache (CB:51620). To have more compact space usage, reduce BOOTBLOCK size from 64K to 60K (only 44K needed), and move starting address of DRAM blob (DRAM_INIT_CODE) to 0x210000 (64K-aligned). BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=asurada Cq-Depend: chrome-internal:3704751 Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-22soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen
Configure SCP domain from 0 to 3 and lock it to prevent changing it unexpectedly. BUG=b:163300760 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17vendorcode/mt8192: devapc: fix register offset for PCIe domainNina Wu
Correct the wrong offset for setting PCIe domain. Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu
The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust "tLOW". 2. modify ext_conf reg to adjust "tSU,STO". BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/mediatek/mt8192: devapc: Add domain remap settingNina Wu
MT8192 devapc supports remapping domains. There may be different domain bit for different subsys. For example, domain bit in INFRA is 4-bit, while in MMSYS, domain bit is 2-bit. For INFRA master to access MM registers, the domain bit will change from 4 to 2 and need to be remapped. In this patch we have remapped: 1. TINYSYS (3-bit to 4-bit) - domain 3 to domain 3 - others to domain 15 2. MMSYS slave (4-bit to 2-bit) - domain X to domain X, for X = 0 ~ 3 - others to domain 0 Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-15mb/google/asurada: revise PMIC and RTC initializationYidi Lin
Move the initialization from bootblock to romstage for following reasons: - Follow MT8183 initialization sequence. - PMIC and RTC functions are only called after verstage. - Reduce bootblock size. - PMIC initialization setting is complex and may need to be changed by an RW firmware update. TEST=boot to kernel successfully Change-Id: I3e4c3f918639590ffc73076450235771d06aae91 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-10soc/mediatek/mt8192: mt6315: revise initial settingHsin-Hsiung Wang
Remove unused boot status settings. Reset the power-off sequence to zero to meet hardware requirement. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Ie9d39be532ec378bd6df6bf1b93307dae4068fc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51246 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/mediatek/mt8192: mt6315: update initial flowHsin-Hsiung Wang
We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence failure, and after checking MT6315 MT6315 PMIC protection key summary.xlsx and MT6315 Top and CLK programming guide.docx, we found there are something wrong about the sequence of magic key protection flow and clk setting. Update correct initial flow. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10soc/mediatek/mt8192: mt6315: update correct slave idHsin-Hsiung Wang
The initial settings for MT6315 were not applied correctly because the setup process didn't specify correct slave id (incorrectly always sending 0), and may cause failure in power off sequence. BUG=b:179000151 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400KYu-Ping Wu
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to 400K. With this change, most part of the DRAM full calibration log can be stored in CBMEM console. BUG=b:181933863 TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=none Change-Id: I896884d298e197149f75865e9d00579124a34404 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08soc/mediatek/mt8173,mt8183: revise SOC DRAM implementationXi Chen
Many header files and helper macros have been moved to the common folder and we want to use them in mt8173/mt8183 DRAM calibration code. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51224 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/mediatek/mt8192: initialize DRAM using vendor reference codeHuayang Duan
Mediatek has released the reference implementation for DRAM initialization in vendorcode/mediatek/mt8192/dramc (CB:50294) so we want to use it to replace the derived calibration code in soc folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen
To reduce duplicated dram sources on seperate SOCs, add dpm, dram_init, dramc_params, memory(fast-k or full-k) implementations, also add dramc log level macro header files. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-25mb/google/asurada: Enable RTC for event logYu-Ping Wu
BUG=b:177399759 TEST=firmware_EventLog passed on asurada BRANCH=none Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-16soc/mediatek: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I7706ffe6f82e3ae2c61cacbea12d94aca48757d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-15soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: If025d4c0b2ba9868d8df699fcddfcec349cdc0ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50529 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu
For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot process. The loading (plus decompression) time of mcupm.bin and sspm.bin is consistently reduced by 8ms, respectively. BUG=b:177389446 TEST=emerge-asurada coreboot TEST=Hayato booted up BRANCH=none Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-04soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS
Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50168 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-01soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K memory, but currently only 208K is reserved for it. Since MT8192 has 1MB SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K. BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Asurada booted successfully BRANCH=none Cq-Depend: chrome-internal:3568265 Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin
Raise little CPU to 2GHz at romstage to improve boot time. BUG=b:177389446 TEST=observe boot time by `cbmem` Before: 1,062,359 us After: 907,458 us Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin
Initialize pmif_arb in romstage. BUG=b:177389446 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I3ffe7277c9ecb04269c832693d42799ba1711384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22soc/mediatek/mt8192: pmic: Set efuses manuallyHsin-Hsiung Wang
Some efuse settings would not be applied automatically, so we need set the settings manually. The low power consumption would not be optimal without correct efuse settings. BUG=b:172636735 BRANCH=none TEST=see 'pmic_efuse_setting: Set efuses in 11 msecs' Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df Reviewed-on: https://review.coreboot.org/c/coreboot/+/49006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22soc/mediatek/mt8183: Fix pq module size configYu-Ping Wu
For pq module size registers such as DISP_AAL_SIZE, the high bits should be HSIZE, while low bits should be VSIZE. Fix the incorrect settings for these registers where width and height are reversed. According to MediaTek, there is no practical impact on mt8183 devices, but it's still nice to get this fixed to avoid future confusion. BUG=b:171167210 TEST=none BRANCH=kukui Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20soc/mediatek/mt8192: pmic: unlock key protection before initial settingHsin-Hsiung Wang
We need to write some special values to key protection registers before applying init_setting table and lp_setting table to PMIC. Otherwise, those settings won't take effect. After applying init_setting table and lp_setting table, we lock the settings by writing zero to key protection registers. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I593d4e02bf0b62ac297957caf4ae1c1837f1f38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-20soc/mediatek/mt8192: pmic: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=none BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df Reviewed-on: https://review.coreboot.org/c/coreboot/+/49355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8173/dramc_pi_calibration_api.c: Use __func__Elyes HAOUAS
Change-Id: I461012b164bbd6f2d1162a793903aafe0b15e234 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-19soc/mediatek/mt8173/pmic_wrap.c: Use __func__Elyes HAOUAS
Change-Id: I3fb4db3fbb72d1444c84b9b66193c26a07561a3f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-19soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown settingHsin-Hsiung Wang
Update the settings of long press shutdown to avoid rtc alarm boot. BUG=b:174546890 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I0841e55674f6b26f355ab678a73d4060fe93f27c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49354 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/mediatek/mt8192: pmic: update initial settingHsin-Hsiung Wang
We found that the switch frequency of vgpu is at 4~5Mhz with high current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A). The switch frequency of vgpu should be kept at 2.5Mhz. The root cause is that phase config of vcore is not disabled, it will affect the switch frequency of vgpu. Corret the phase setting at initialization. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49005 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driverYuchen Huang
Add clkbuf and srclken_rc init for low power. Reference datasheet: Document No: RH-D-2018-0205. TEST=boot asurada Signed-off-by: Ran Bi <ran.bi@mediatek.com> Change-Id: I947bf14df7a307bf359c590c2a20265882b3f1be Reviewed-on: https://review.coreboot.org/c/coreboot/+/46878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Save dramc shuffle result after calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Add dramc ac timing settingHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Get DDR base information after calibrationHuayang Duan
After calibration, we can get ddr vendor id or density info from MR5 or MR8, this helps to make sure the DDR HW is as we expected. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-15soc/mediatek/mt8183: Support byte mode and single rank DDRShaoming Chen
1. Add emi setting to support byte mode and single rank ddr sample 2. Modify initial setting for DDR with different architecture BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07soc/mediatek: rtc: Use `bool` as return typeYidi Lin
BUG=b:176307061 TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot boot to shell on Asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-01soc/mediatek: dsi: Fix EoTp flagShaoming Chen
SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin
The flash controller driver can be shared among mt8173 and mt819x. TEST=boot to kernel on Asurada boot to kernel on Hana (w/o BL31) Change-Id: I4e5213563189336496122a0f2d8077b3e5245314 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-31soc/mediatek/mt8192: Add DDR mode register initHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan
To get better PI linearity, perform 8 phase calibration to do MCK 0/180/45 training and select the best PI settings. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-30soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao
eint event mask register is used to mask eint wakeup source on mt8192. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel eint upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. BUG=b:169024614 Signed-off-by: G.Pangao <gtk_pangao@mediatek.com> Change-Id: I8ee80bf8302c146e09b74e9f6c6c49f501d7c1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46409 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-28soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor mt8173 and mt8183 code by extracting common API. Move rtc_read and rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via pmic wrapper, while mt8192 accesses it via pmif. Reference datasheet: Document No: RH-D-2018-0101. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-22soc/mediatek/mt8192: Do dramc software impedance calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-22soc/mediatek/mt8192: Do EMI init before dram calibrationHuayang Duan
Reference datasheet: External Memory Interface (EMI).pdf, Document No: RH-A-2020-0055. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-22soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan
Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-16soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang
The voltage of vm18 should be microvolt instead of millivolt. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Keep CONN MCU in reset stateWeiyi Lu
Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Do dramc init settingsHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Enable DCMmtk15698
Enable DCM settings. Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Signed-off-by: mtk15698 <michael.kao@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: ufs: Disable reference clockWenbin Mei
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Initialize audio pll tuner frequencyWeiyi Lu
Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15soc/mediatek/mt8192: Define DRAM registers and APIsHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ifc64fb6c60d57184c4a2f9febe765b5cb69b39ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/44699 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8192: Add ddp driverYongqiang Niu
Add ddp (display controller) driver that supports overlay, read/write DMA, etc. The output goes to display interface DSI, DPI or DBI directly. BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46577 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8192: Enable dsi driverHuijuan Xie
Enable dsi driver for display. BUG=b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46574 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14soc/mediatek/mt8183: Move dsi driver to common/Yidi Lin
The mt8183 dsi driver can be shared with mt819x SoC. Move dsi.c to common/ folder and rename it to dis_v2.c to differentiate it from mt8173's dsi driver. TEST=emerge-kukuki coreboot Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-14soc/mediatek/mt8192: add i2c driver supportQii Wang
Add I2C controller for MT8192, and revise the common I2C driver to support I2C controller running in APDMA async mode. In that case we have to initiate a different handshake protocol and reset I2C differently. BUG=b:155715435 TEST=Asurada boots up to shell Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/mt8192: Init SSPMTingHan.Shen
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com> Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
DPM is a hardware module for DRAM power management and for better power saving in low power mode. BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPMYidi Lin
MCUPM is the MediaTek proprietary firmware for MCU power management. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes 3. Test suspend/resume by: a. suspend (on DUT): powerd_dbus_suspend b. resume (on host): dut-control power_state:on Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46392 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10soc/mediatek/mt8192: add spmfw loaderRoger Lu
This patch adds support for loading spm firmware from cbfs to spm sram. Spm needs its own firmware to enable spm suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. BUG=b:159079649 TEST=suspend with command `powerd_dbus_suspend` and wake up the DUT by powerkey Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/mt8183: Use mtk_init_mcu to init SSPMYidi Lin
Use mtk_init_mcu API to load and run sspm firmware. TEST=emerge-kukui coreboot Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/mt8183: Add DRAM_DMA sectionYidi Lin
mtk_init_mcu uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtk_init_mcu. On mt8173 and mt8192, this region is used by DMA hardware and is marked as non-cacheable resource. On mt8183, this region is reserved as CBFS buffer, so it is not necessary to be marked as non-cacheable resource. Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10soc/mediatek/common: Add common API for loading firmwaresYidi Lin
Add mtk_init_mcu to load the firmware to the specified memory address and run the firmware. This function also measures the load time and the blob size. For example: mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes) Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-20mediatek/mt8192: memlayout: Add DRAM DMA regionYidi Lin
SPM DMA hardware requires a non-cacheable buffer to load SPM firmware. TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-20soc/mediatek/mt8192: Enable MT8192 auxadc driverPo Xu
Enable reading from auxadc on MediaTek 8192 platform. Reference datasheet: RH-A-2020-0070, v1.0 Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-11-20soc/mediatek: Move auxadc driver from MT8183 to commonPo Xu
The auxadc (auxiliary analogue-to-digital conversion) is a unit to identify the plugged peripherals or measure the temperature or voltages. The MT8183 auxadc driver can be shared by multiple MediaTek SoCs so we should move it to the common folder. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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