coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-10-14	soc/mediatek/mt8186: Inititalize ADSP	Tinghan Shen
	To use SOF correctly, we need to initialize ADSP in coreboot stage. TEST=SOF driver is functional. BUG=b:204229221 Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-26	soc/mediatek: Do resource transition	Kyösti Mälkki
	Change-Id: I668a39c603870329fd1528ddc5f3a42a379e1e76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65267 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22	device/resource: Add _kb postfix for resource allocators	Kyösti Mälkki
	There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-18	soc/mediatek: Set soc_ops.set_resources as no-op	Yu-Ping Wu
	Without setting the set_resources field for soc_ops, we will get an error during device initialization: [ERROR] CPU_CLUSTER: 0 missing set_resources Because the set_resources field is considered mandatory, explicitly set it as no-op noop_set_resources. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Did not see the error on krabby BRANCH=none Change-Id: Ic82b86f0482a9de09e942c1674be5f0ac615851f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-01-07	soc/mediatek/mt8186: initialize DFD	Rex-BC Chen
	DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7b711755022b5d9767019611151fea65e71edc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-28	soc/mediatek/mt8186: Add devapc basic drivers	Runyang Chen
	Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17	soc/mediatek/mt8186: initialize SSPM	Rex-BC Chen
	SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15	soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA	Rex-BC Chen
	1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03	soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC	Rex-BC Chen
	Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>