coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-08-06	soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootup	Huayang Duan
2020-08-06	soc/mediatek/mt8183: Add missing register settings for channels	Huayang Duan
2020-05-20	soc/mediatek/mt8183: Set CA and DQ vref range to correct value	Huayang Duan
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-05	soc/mediatek: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2019-12-04	Change all clrsetbits_leXX() to clrsetbitsXX()	Julius Werner
2019-10-28	soc/mediatek/mt8183: Pass MR values as function arguments	Yu-Ping Wu
2019-10-18	soc/mediatek/mt8183: Pass impedance data as a function argument	Yu-Ping Wu
2019-10-18	soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switch	Huayang Duan
2019-10-17	soc/mediatek/mt8183: Remove unnecessary DRAM register settings	Yu-Ping Wu
2019-10-17	soc/mediatek/mt8183: Fix DDR phy config number	Yu-Ping Wu
2019-10-17	soc/mediatek/mt8183: Refactor DRAM init by bit fields API	Hung-Te Lin
2019-10-17	soc/mediatek/mt8183: Improve code formatting	Yu-Ping Wu
2019-10-09	soc/mediatek/mt8183: Use cached calibration result for faster bootup	Huayang Duan
2019-09-20	mediatek/mt8183: Implement the dramc init setting	Huayang Duan
2019-06-21	mediatek/mt8183: fix mode register setting fail issue	Huayang Duan
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2018-10-24	mediatek/mt8183: Initialize DRAM with a sequence in constant array	Huayang Duan