| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-19 | soc/lowrisc: Remove the remains of a LowRISC soc | Peter Lemenkov |
| 2018-09-26 | mb/lowrisc: Remove the Nexys4DDR port | Jonathan Neuschäfer |
| 2018-09-14 | arch/riscv: provide a monotonic timer | Philipp Hug |
| 2018-09-10 | soc/sifive/fu540: Makefile: include mtime_init in ramstage | Philipp Hug |
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang |
| 2018-07-17 | riscv: add support for modifying compiler options | Xiang Wang |
| 2017-11-07 | RISC-V boards: Stop using the config string | Jonathan Neuschäfer |
| 2017-10-23 | soc: Add Kconfig for each soc vendor | Chris Ching |
| 2016-12-06 | soc/lowrisc: Place CBMEM at top of autodetected RAM | Jonathan Neuschäfer |
| 2016-10-25 | riscv: add the lowrisc System On Chip support | Ronald G. Minnich |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |