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2023-08-06soc/intel/common/tcss: Configure USB-C ports with attached devicesCoolStar
Inspect all type-C USB ports, check if there is a USB device attached, and if so, send the connection request to the PMC. This allows for any attached USB2/USB3 devices to be used for booting by the payload. Since this functionality is only needed by ChromeOS devices with TCSS running upstream coreboot, introduce a new Kconfig to guard its use. Boards needing it will select it in subsequent commits. TEST=tested with rest of patch train Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06soc/intel/common/block/tcss: Fix printk formattingMatt DeVillier
Variable 'i' is unsigned, so use %zu vs %zd. Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotionSukumar Ghorai
FSP has a parameter to enable/disable c1-state autodemotion feature. Boards/Baseboard can choose to use this feature as per requirement. This patch hooks up this parameter to devicetree. BUG=b:286328295 TEST=Check code compiles & boot google/rex, and correct value has been passed to FSP. Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04soc/intel/mtl: Change default for debug consent from 3 to 6Kane Chen
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled. This patch updates the Kconfig help text to meet PlatformDebugOption in MTL and changes debug consent to 6 in default to provide basic SoC debug capability. TEST=Boot to OS on screebo and DBC connection is OK. Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat
cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04soc/intel/meteorlake: Generate new TME key on each warm bootPratikkumar Prajapati
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor Lake SOCs. This config allows Intel FSP to programs TME engine to generate a new key for each warm boot and exclude CBMEM region from being encrypted by TME. Bug=b:276120526 TEST= Boot up the system, generate kernel crash using following commands: $ echo 1 > /proc/sys/kernel/sysrq $ echo "c" > /proc/sysrq-trigger System performs warm boot automatically. Once it is booted, execute following commands in linux console of the DUT and confirm ramoops can be read. $ cat /sys/fs/pstore/console-ramoops-0 S0ix also tested and found working. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-03soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas
Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHNElyes Haouas
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVERElyes Haouas
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUTElyes Haouas
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/meteorlake: Set UPDs for TME exclusion range and new key genPratikkumar Prajapati
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properlyMichał Żygowski
Build issue introduced by patch CB:76418 (commit hash 01025d3ae78e02192d389f22abd36747e3d8c63b) for Google boards. Patch has not been rebased to latest master and tested before submission causing the Jenkins jobs to fail. Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbolMichał Żygowski
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected by board with RPL-S PCH. For now only the IoT variant of RPL-S FSP is available for use with 700 series chipsets. Boards with 600 series chipsets can still use RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU support. Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPOMichał Żygowski
Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-08-01soc/intel/broadwell/include/soc/me.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01soc/intel/common/mma: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id19193b960935eeffca8e8db60073321592368fe Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31soc/intel/apl: Hide PMC/IPC ACPI device from WindowsMatt DeVillier
No drivers are needed/available, so hide the device to prevent an unknown device from showing under Device Manager. Linux does not use the ACPI _STA so no effect there. Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31soc/intel/apl: program VMX per Kconfig settingMatt DeVillier
While FSP programs the VmxEnable UPD per CONFIG_ENABLE_VMX, it doesn't set the lock bit, which prevents Windows from enabling virtualization on devices which support it. Call set_vmx_and_lock() to ensure the lock bit is properly set. TEST=build/boot Win11 on google/ampton,reef; verify virtualization enabled. Change-Id: I54ea0adb0a6d10f2df18f604b1f1e5a7a145dfb3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76804 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-31soc/intel/alderlake: Allow channel 0 for DDR5 memory-downJeremy Soller
This matches the change done for DDR4 in commit 8509c25eece8 ("soc/intel/alderlake: Allow channel 0 for memory-down"). Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only boards in the tree using mixed memory topology. Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31soc/intel/common/block/pcr: Remove useless break after a returnElyes Haouas
Change-Id: Ie7f2144d0af21ba111464dfd135159704a3d82b7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76474 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31soc/intel/alderlake/hsphy.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-30soc/intel/broadwell/pch/me.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iea63e7ce165b1c8129725136e39bff45765023e6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-25soc/intel/meteorlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I0f9299d4b7417efac0d5fba39d40b97d6c3a1926 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-25soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set AllowedSocketsInParallel to 1 for RMT builds. This help in associating any failures encountered during RMT run with the corresponding Socket/MC/DIMM. Intel recommended setting EnforcePopulationPor to 1 for RMT runs for debugging failures if any. Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-21soc/intel/alderlake: Hook up UPD PchHdaSdiEnableBora Guvendik
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:268546941 TEST=Verified the settings on google/brya using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-20soc/intel/xeon_sp: use VGA_MMIO_* defines from arch/vga.hFelix Held
Now that we have x86 architecture specific VGA_MMIO_* defines in arch/vga.h, use those instead of having SoC-specific defines for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77b914d563bdc83e7fad7d7fccd5cf7777cb4918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-20acpi: Move ECAM resource below PNP0C02 device in a common placeArthur Heymans
From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-19soc/intel/alderlake: Use 1MB CBMEM console buffer with FSP debugSubrata Banik
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log. The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or not. Ideally. larger cbmem size is required only if FSP debug is enabled. Bug=b:284124701 TEST=Able to build and boot google/marasov. Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-19soc/intel/{adl, mtl}: Reduce CAR usage while using FSP debug binariesSubrata Banik
Reduces the CAR (Cache-as-RAM) variable usage while using FSP debug binaries, which can prevent the CAR from becoming too full and unable to integrate other CAR global variables. This change has the following downsides: - FSP debug output into the cbmem buffer will be partial. To test this change, you can: Build and boot google/rex without any function impact with non-serial and serial FSP debug image (unless what has been documented here). Bug=b:284124701 TEST=Able to build and boot google/rex. Change-Id: I16a1aa25fd32327d03a37381a696c86c95014ba0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/alderlake: Hook up CsPiStartHighinEct UPDKane Chen
This commit provides option for board to set CsPiStartHighinEct FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field. BUG=b:279835630 BRANCH=none TEST=CsPiStartHighinEct UPD is set properly Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18soc/intel/xeon_sp: Skip empty socketsPatrick Rudolph
The current Sapphire Rapids code assumes that all sockets have working CPUs. On multi-socket platforms a CPU might be missing or was disabled due to an error. The variable PlatformData.numofIIO and the variable SystemStatus.numCpus reflect the working CPUs, but not the actual socket count. Update the code to iterate over sockets until PlatformData.numofIIO IIOs have been found. This is required as FSP doesn't sort IIOs by working/non working status. This resolves invalid ACPI table generation and it fixes a crash as commands were sent to a disabled CPU. TEST: Disabled Socket1 on IBM/SBP1. Change-Id: I237b6392764bbdb3b96013f577a10a4394ba9c6e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76559 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/xeon_sp: Use SocketID in NUMA table generationPatrick Rudolph
Use the actual SocketID instead of the running index. Change-Id: I9128909756d0dbb0c4dabc52acdc98cb2a4f7baa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/xeon_sp: Remove invalid commentPatrick Rudolph
The comment is only true if all sockets have working CPUs installed. Change-Id: I8c3376c9233c33fb770082573e07e9d96abb7855 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76557 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/xeon_sp: Introduce soc_cpu_is_enabledPatrick Rudolph
Add a function to check if the CPU placed at the specified socket was found usable during QPI init. This is useful for multi-socket platforms were a CPU is missing or has been disabled due to an error. Change-Id: I135968fcc905928b9bc6511e3ddbd7d12bad0096 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/xeon_sp: Print HOB for all socketsPatrick Rudolph
Use the FSP define to iterate over all sockets as the runtime value of numofIIO is the detected number of sockets, not the highest working socket. This fixes printing the HOB on multi-socket platforms where a CPU has been removed or has been disabled (4S system running as 3S). Change-Id: Ieed67cd48d26c7634636c0aae6a56f3b6fbdf640 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76492 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/meteorlake: Enable PCIE_CLOCK_CONTROL_THROUGH_P2SBKane Chen
On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by P2SB on IOE/SOC die. So this patch does: 1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB 2. Include pcie_clk.asl 3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H. BUG=b:288976547, b:289461604 TEST=Test on google/screebo and found the pcie clock is on/off properly and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled. Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/common/acpi: Support on/off PCIe CLK by P2SBKane Chen
In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it needs PMC IPC cmd to turn on/off the corresponding clock. Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on IOE or SoC die. BUG=b:288976547, b:289461604 TEST=Test on google/screebo and found the pcie clock is on/off properly and sdcard pcie port doesn't block S0ix with RTD3 cold enabled. Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/meteorlake: Include IOE PCR register accessSubrata Banik
This patch includes the ioe_pcr.asl file as Intel Meteor Lake has support for IOE die. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Ia534dbc0db5e54e173da9cdf475a7eb2bfda9e2f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76410 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-18soc/intel/common/acpi: Add IOE PS2B access APIsSubrata Banik
This patch implements APIs to access PCR registers from IOE die. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Ief7a00c4e81048f87ee308e659faeba3fde4c9cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76409 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-07-18soc/intel/meteorlake: Add IOE P2SB Base AddressSubrata Banik
This patch introduces a new config named IOE_PCR_BASE_ADDRESS to define P2SB base address. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: I289358f9c53b557a397bd7186e6b7419c5d8c954 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76411 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/common/acpi: Create helper APIs for common P2SB accessSubrata Banik
This patch creates a helper library to migrate all the common P2SB access routines. The PCH P2SB ACPI implementation will now rely on the common library to perform PCR read/write operations. This will make the code more modular and easier to maintain. The helper library provides a single interface for accessing P2SB registers. This makes it easier to port the code to different platforms, for example: adding support for PS2B belongs to the IOE die for Meteor Lake SoC generation. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: I0b2e7ea416ca7082f68d0b822ebb9a87025b4a8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76408 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/intel/adl: Add power limits for RPL-H 4P+8E 45WTim Crawford
Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1) Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-17soc/intel/denverton: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id092b6dd9d42f2965801b0327a857a5a4945f793 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76288 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15soc/intel/common: Add support for AP initiated mode entryKapil Porwal
Add support for AP initiated mode entry. The code flow has been optimized as below - Code flow when AP initiated mode entry is disabled: +-------+ | Start | +---+---+ | | +---------+---------+ |wait_for_connection| | Is DP ALT mode | | available? | +---------+---------+ | +--------------->-------+ Yes| No | +---------+---------+ | |Skip enter_dp_mode | | +---------+---------+ | | | | | +-----------+----------+ | |wait_for_dp_mode_entry| | | Is DP flag set? | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | wait_for_hpd | | | Is HPD_LVL flag set? | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | Rest of the code | | +-----------+----------+ | | | +---------------<-------+ | +---+---+ | End | +-------+ Code flow when AP initiated mode entry is enabled: +-------+ | Start | +---+---+ | +------------+-----------+ |Skip wait_for_connection| +------------+-----------+ | +--------+-------+ | enter_dp_mode | | Is USB device? | +--------+-------+ | +--------------->-------+ Yes| No | +---------+---------+ | | enter_dp_mode | | | Send DP mode | | | entry command | | +---------+---------+ | | | +-----------+----------+ | |wait_for_dp_mode_entry| | | Is DP flag set? | | | (If not, loop wait | | | until timed out) | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | wait_for_hpd | | | Is HPD_LVL flag set? | | | (If not, loop wait | | | until timed out) | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | Rest of the code | | +-----------+----------+ | | | +---------------<-------+ | +---+---+ | End | +-------+ BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Time taken by enter_dp_mode / wait_for_dp+hpd / MultiPhaseSiInit functions with this patch train: 1. When AP Mode entry is enabled - With type-c display on C1 and SuzyQ on C0: 6.9ms / 420ms / 616ms - With USB key on C1 and SuzyQ on C0 : 6.0ms / 505ms / 666ms - Without any device on C1 and SuzyQ on C0 : 3.7ms / 0ms / 178ms 2. When AP Mode entry is disabled - With type-c display on C1 and SuzyQ on C0: 1.7ms / 2.5ms / 213ms - With USB key on C1 and SuzyQ on C0 : 0.9ms / 3.3ms / 177ms - Without any device on C1 and SuzyQ on C0 : 0.8ms / 1.8ms / 165ms Without this patch train, wait_for_hpd would cause a constant delay of WAIT_FOR_HPD_TIMEOUT_MS (i.e. 3 seconds) per type-c port when there is no device connected. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I514ccbdbaf905c49585dc00746d047554d7c7a58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-14soc/intel/cannonlake: Hook up ucode for CML-STim Crawford
Hook up microcode from 3rdparty repo for: - 06-a5-03 (CPUID signature: 0xa0653) - 06-a5-05 (CPUID signature: 0xa0655) Fixes loading microcode on system76/bonw14. Change-Id: Ie6789420926fe46fc61ea6773f02dc07dc2e9b5e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-14soc/intel/adl: Add Raptor Lake-HX definitionsTim Crawford
Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13) to edk2 payload and then OS. Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8) Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-13soc/intel/braswell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4769f79c67c372e11bb267de3acec0920d7ab0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-13soc/intel/baytrail: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80c8a1b58e8102ed11e22b74f30750d5a6c4eae4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76283 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Disable hwp scalibility trackingBora Guvendik
Disable scalability tracking for autonomous frequency control in order to improve power and performance. BUG=b:280021171 TEST=Boot to OS on brya0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTrackingBora Guvendik
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that boards can configure is via devicetree. BUG=b:280021171 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-13soc/intel/alderlake: Hook up UPD DisableSagvReorderBora Guvendik
Hook the newly exposed DisableSagvReorder UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-07-13soc/intel/alderlake: Disable SaGV reorderingBora Guvendik
Disable re-ordering SaGv point on warm reset so that most performant SaGv point is picked after memory training and boot time is reduced. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13soc/intel/alderlake: Reduce memory test sizeBora Guvendik
Enable upd to reduce size of the memory test. BUG=b:268546941 TEST=Observe boot time improvement with these two UPDs set Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-13soc/intel/alderlake: Hook up UPD LowerBasicMemTestSizeBora Guvendik
Hook the newly exposed LowerBasicMemTestSize UPD up so that boards can configure is via devicetree. BUG=b:268546941 TEST=Verified by enabling/disabling the UPD on google/brya Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12soc/intel/common: Restore to page 0 before reading SPDCoolStar
test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee Verify memory type detected properly and following boot works Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-12intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match tableMichał Żygowski
Only A step ADL-S CPUs were added to CPU table for MP init. Add the remaining ADL-S CPUs to the table. TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot no longer uses generic CPU ops. Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset nameMichał Żygowski
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12soc/intel: Fix W790 chipset nameMichał Żygowski
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A belongs to the W790 chipset. Earlier revisions had the chipset with ID 0x7A8A named W685, which was probably just a temporary name. Change the naming throughout the tree to W790, which is the real existing chipset. Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz
Add PCI IDs, default VR values and power limits for Raptor Lake S CPUs. Based on docs 639116 and 640555. TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu 22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock@googlemail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-07-12soc/intel/adl: Reduce microcode redundancyNico Huber
Some of the microcode update files listed in the Makefile are redundant: * 06-97-02 is exactly the same as 06-97-05 * 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400) So drop these files. This saves us about 200KiB CBFS space in each case. Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-12soc/intel/*/pmc.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-12soc/intel/common: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If7fe96220ce5b13f5541e25935afd0c681ff40f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76286 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/apl: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5728dc144b0d04a92a1e0a4b9abbe17ef0a06e41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76282 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12soc/intel/broadwell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie44518988e999794fba35f41075ff62e82663d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76285 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11soc/intel/xeon_sp: Clear reserved field in SRATNaresh Solanki
During the ACPI dump of the System Resource Affinity Table (SRAT), it was noticed that the reserved field within the Memory Affinity structure contained a non-zero value. This commit addresses the issue by performing a memset to zero on the reserved field, ensuring the avoidance of any potential problems arising from garbage values. TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries reserved fields read zeroes Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-07soc/intel/xeon_sp/spr: Fix upd_display.c build errorJohnny Lin
Fix below build error after DISPLAY_UPD_DATA is selected: src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable] 131 | const FSP_S_CONFIG *old; | ^~~ src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable] 130 | const FSP_S_CONFIG *new; Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-07-05soc/intel/alderlake: Increase default CBFS size to 4MBFelix Singer
Updating some submodule pointers to their latest commit causes some builds with default configuration to fail since all required components don't fit into 2MB anymore. Specifically, this has been experienced with the microcode and FSP submodules. So, increase the default CBFS size to 4MB to make sure builds succeed with updated submodules. Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteorlake: add power limits for 28W SKUSumeet Pawnikar
Add power limit values for Meteor Lake 28W SKU. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05soc/intel/meteoerlake: add support for 28W SKUSumeet Pawnikar
Add power limits support for 28W SKU. BRANCH=None BUG=b:289854108 TEST=Build FW Change-Id: I83deb1e574990cb70f9aac5d5eb46fbb710a6170 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76238 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-03Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cseMatt DeVillier
Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-29soc/intel/meteorlake: remove unused tcss mailbox codeKane Chen
In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE So, this patch removes unused code related to MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE ADL also removes this code, see cl:62861 BUG=b:288976547 TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-29soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi
This patch adds CPU ID for C0 stepping (aka QS). DOC=#723567 TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log. Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28intelblocks/pep: Send All Monitor Off/On command only in FWCM caseUsha P
ALL_MONITOR_OFF command is sent using DPOF. TBT controller needs to be notified about ALL_MONITOR_OFF(TBT Displays OFF) only when Firmware Connection Manager(FWCM) is in use during S0ix Entry/Exit. When configured for SWCM this command should not be sent. BUG=b:288536417 TEST= Build and boot Rex Proto-1. Verify S0ix working. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75717 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Utkarsh H Patel <utkarsh.h.patel@intel.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26soc/intel/common: Print crashlog size info in hexPratikkumar Prajapati
Print crashlog size information in hex to be consistent with other prints. BUG=b:262501347 TEST=Values printed in hex. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75910 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-26soc/intel/meteorlake: Add support for crashlogPratikkumar Prajapati
Capture crashlog records from CPU PUNIT SRAM, SOC PMC SRAM and, IOE SRAM. Crashlog records for IOE SRAM is discovered by parsing SOC PMC SRAM records. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-24soc/intel/cannonlake/chip.h: Use boolean type where applicablelilacious
Change-Id: If9639bd1d0737f94931c28b0e12f214a5c1f87c0 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75959 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-24soc/intel/skylake/chip.h: Use boolean type where applicableFelix Singer
Change-Id: Ic40917689092e8d897a3ba92ac767cdb3b595eb3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75880 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/intel/jasperlake: Add per-SKU power limitsChia-Ling Hou
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni@intel.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23soc/intel/common/block/cse: Retrieve CSE RW FW version conditionallySubrata Banik
This patch introduces a newer config to store the CSE RW FW version into the CBMEM. Prior to that CSE RW FW version was fetched unconditionally and ended up increasing the boot time by 7ms to 20ms depending on the SoC arch (including CSE arch). The way to retrieve the CSE firmware version is by sending the HECI command to read the CSE Boot Partition (BP) info. The cost of sending HECI command to read the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,ensure this feature is platform specific and only enabled for the platformthat would like to store the CSE version into the CBMEM. TEST=Build and boot google/rex to avoid getting CSE RW FW version to save 18ms of the boot time. w/o this patch:   10:start of ramstage                            722,215 (43)   17:starting LZ4 decompress (ignore for x86)     741,415 (19,200) w/ this patch:   10:start of ramstage                            722,257 (43)   17:starting LZ4 decompress (ignore for x86)     723,777 (1,520) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-06-23soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flashMichał Żygowski
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20treewide,intel/skylake: Use boolean type for s0ix_enable dt optionFelix Singer
Using the boolean type and the true/false macros give the reader a better understanding about the option. Thus, use the bool type for the attribute and use the macros for assignments. Skylake mainboards which use that option were changed by the following command ran from the root directory. socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \ option="s0ix_enable" && \ grep -Er "${socs}" src/mainboard | \ cut -d ':' -f 1 | \ awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \ xargs grep -r "${option}" | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-06-19soc/intel/cometlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74517 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19cbfs: Allow controlling decompression of unverified filesJulius Werner
This patch adds a new Kconfig that controls whether CBFS APIs for unverified areas will allow file decompression when CBFS verification is enabled. This should be disallowed by default because it exposes the attack surface of all supported decompression algorithms. Make allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_ COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75457 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPwrOptimizeDisable'. Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75859 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableSataSalpSupportMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableSataSalpSupport'. Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicVdd2VoltageMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicVdd2Voltage'. Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75857 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 05:29:04 +0000