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2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyVoltageBumpMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for ModPhyIfValueMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for DisableComplianceModeMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'DisableComplianceMode'. Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrlMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'PmicPmcIpcCtrl'. Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Switch to snake case for SataPortsHotPlugMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsHotPlug'. Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75852 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19soc/intel/apollolake: Fix FSP SATA speed limit configuraionMario Scheithauer
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit configurable") came the expansion to adjust the SATA speed. Unfortunately, APL FSP-S sets only the default value, so Gen 3, and ignores the passing parameter value. Since the corresponding register entry can only be changed once, the setting must be made on coreboot side before FSP-S is called. This patch fixes the SATA speed configuration for Apollo Lake CPUs. Link to Intel Pentium and Celeron N- and J- series datasheet volume 2: https://web.archive.org/web/20230614130311/https://www.intel.com/content/www/us/en/content-details/334818/intel-pentium-and-celeron-processor-n-and-j-series-datasheet-volume-2.html BUG=none TEST=Boot into Linux and check SATA configuration via dmesg ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA mode ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126 ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75820 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-16soc/intel/meteorlake: select UDK_202302_BINDING KconfigRonak Kanabar
MTL FSP uses 202302 Edk2. select UDK_202302_BINDING Kconfig for MTL SoC. BUG=b:261689642 TEST= Build and boot to Google/rex. Change-Id: I9167e3b08a2a1fa2f4cc6ca11cb8308dc56fd940 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75728 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16soc/intel/common: Add configs for TME exclusion range and new key genPratikkumar Prajapati
Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION This option allows to exclude the CBMEM region from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM region does not get encrypted by TME. If TME is not programmed to generate a new key in warm boot, exclusion range does not need be programmed due to the fact that TME uses same key in warm boot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm boot, contents of the CBMEM get encrypted with a new key in each warm boot case hence, that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM region to get excluded from being encrypted and can be accessible irrespective of the type of the platform reset. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75625 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMCSubrata Banik
This patch disables the ACPI PM timer which is necessary for XTAL OSC shutdown. Also, disabling ACPI PM timer switches off TCO. BUG=b:274744845 TEST=Able to boot and verify S0ix is working even with EC reset and cold boot scenarios. w/o this cl: > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15soc/intel: Add max memory speed into dimm infoEric Lai
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bitsMichał Żygowski
Based on: - Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 - 7th Generation Intel Processor Families I/O for U/Y Platforms Datasheet Vol.2 August 2017: https://cdrdv2.intel.com/v1/dl/getContent/334659 - edk2-platforms source for Whitley and Purley platforms (Xeon SP) Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partitionSubrata Banik
This patch reduces the redundant config check to understand if an ISH FW partition is available and to fetch the ISH FW version. The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE firmware partition table. Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`Dinesh Gehlot
This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Firmware Version:" [DEBUG] CSE RW Firmware Version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/cmn/cse: Always save CSE RW version to CBMEMSubrata Banik
This patch renames `cse_store_rw_fw_version` function that store currently running CSE RW FW version inside CBMEM. Additionally, perform the CSE RW FW storing operation unconditionally. TEST=Able to build and boot google/marasov. Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15{driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-14soc/intel/alderlake/vr_config.c: Fix GT domain TDC currentMichał Żygowski
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder Lake-S SKUs have GT TDC of 22A. Based on the default settings of ADL-S FSP. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-14soc/intel/xeon_sp: Fix HEST table lengthJeff Li
"current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01@inspur.com> Signed-off-by: Ziang Wang <ziang.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07soc/intel/common: Make get_ramtop_addr non staticPratikkumar Prajapati
Make get_ramtop_addr not static to allow other code to use it. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I8ef8a65b93645f25ca5e887342b18679d65e74b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06soc/intel/xeon_sp/spr: Add RMT configNaresh Solanki
This commit adds a configuration option to enable RMT in the coreboot build for the Intel Xeon SP SPR platform. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-06soc/intel/meteorlake: Fill PCI SSID parametersKapil Porwal
Set SSID UPD to program DID as SSID for all the on board PCIe devices if SSID is not being overridden by CONFIG option or device tree. BUG=b:263846223 TEST=Verify that SSID for all PCI devices is same as their respective DIDs. Output of lspci in the OS: 00:00.0 0600: 8086:7d02 (rev 01) Subsystem: 8086:7d02 00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller]) Subsystem: 8086:7d45 00:04.0 1180: 8086:7d03 (rev 01) Subsystem: 8086:7d03 00:05.0 0480: 8086:7d19 (rev 01) Subsystem: 8086:7d19 00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e4d Capabilities: [98] Subsystem: 8086:7e4d 00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec4 Capabilities: [90] Subsystem: 8086:7ec4 00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode]) Subsystem: 8086:7ec6 Capabilities: [90] Subsystem: 8086:7ec6 00:0a.0 1180: 8086:7d0d (rev 01) Subsystem: 8086:7d0d 00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI]) Subsystem: 8086:7ec0 00:0d.2 0c03: 8086:7ec2 (prog-if 40) Subsystem: 8086:7ec2 00:0d.3 0c03: 8086:7ec3 (prog-if 40) Subsystem: 8086:7ec3 00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI]) Subsystem: 8086:7e7d 00:14.2 0500: 8086:7e7f (rev 01) Subsystem: 8086:7e7f 00:14.3 0280: 8086:7e40 (rev 01) Subsystem: 8086:0094 00:15.0 0c80: 8086:7e78 (rev 01) Subsystem: 8086:7e78 00:15.1 0c80: 8086:7e79 (rev 01) Subsystem: 8086:7e79 00:15.3 0c80: 8086:7e7b (rev 01) Subsystem: 8086:7e7b 00:16.0 0780: 8086:7e70 (rev 01) Subsystem: 8086:7e70 00:19.0 0c80: 8086:7e50 (rev 01) Subsystem: 8086:7e50 00:19.1 0c80: 8086:7e51 (rev 01) Subsystem: 8086:7e51 00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode]) Subsystem: 8086:7e3e Capabilities: [98] Subsystem: 8086:7e3e 00:1e.0 0780: 8086:7e25 (rev 01) Subsystem: 8086:7e25 00:1e.3 0c80: 8086:7e30 (rev 01) Subsystem: 8086:7e30 00:1f.0 0601: 8086:7e04 (rev 01) Subsystem: 8086:7e04 00:1f.3 0401: 8086:7e28 (rev 01) 00:1f.5 0c80: 8086:7e23 (rev 01) Subsystem: 8086:7e23 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-04lib: Support localized text of memory_training_desc in ux_locales.cHsuan Ting Chen
To support the localized text, we need to get the locale id by vboot APIs and read raw string content file: preram_locales located at either RO or RW. The preram_locales file follows the format: [string_name_1] [\x00] [locale_id_1] [\x00] [localized_string_1] [\x00] [locale_id_2] [\x00] [localized_string_2] ... [string_name_2] [\x00] ... This code will search for the correct localized string that its string name is `memory_training_desc` and its locale ID matches the ID vb2api returns. If no valid string found, we will try to display in English (locale ID 0). BUG=b:264666392 BRANCH=brya TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04soc/intel/meteorlake: Apply PCIe RP mask based on SoC typeSubrata Banik
This patch ensures to update the FSP-M UPDs related to PCIe RP mask properly as per the SoC type. For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse PCIe RPs are from PCH die in case of MTL-S. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: Ice81553274682476bb4c927061b1196dc142836d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-04soc/intel/meteorlake: Introduce different SoC flavors of Meteor LakeSubrata Banik
This patch introduces the different SoC flavors of Intel Meteor Lake as: * MTL-U * MTL-P * MTL-S MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die. The task for mainboard is to specify the correct SoC type rather than selecting the MTL SoC by default. This change is necessary to support the different SoC flavors of Intel Meteor Lake. BUG=b:276697173 TEST=Able to build and boot google/rex. Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04soc/intel/meteorlake: Hook up UPD PchHdaSdiEnableRonak Kanabar
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:273962021 TEST=Verified the settings on google/rex using debug FSP logs. Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-02soc/intel/apollolake: Switch to snake case for SataPortsEnableMario Scheithauer
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01soc/intel/jasperlake: Enable early caching of RAMTOP regionSean Rhodes
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-01soc/intel/apollolake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's APL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01soc/intel/apollolake: Make SATA speed limit configurableMario Scheithauer
In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SpeedLimit' allows to set the speed limit. It should be noted that Gen 3 equals the default value '0'. This means that inside FSP the same code is executed. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check cbmem pointer before copying recordsPratikkumar Prajapati
Check existence of crashlog records in CBMEM before copying them to BERT, otherwise it can lead to NULL pointer access. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4288011866283a3a5fb8ec9e10cd51b794052b4e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75528 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01soc/intel/common/crashlog: Check for invalid recordPratikkumar Prajapati
Do not copy the crashlog record if the record is 0xdeadbeef Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I0edbf6902685a882876d525e63c5b602c1590ea1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01soc/intel/common/crashlog: Fix checking PMC record sizePratikkumar Prajapati
Check pmc_record_size variable for collecting PMC records, instead of cpu_record_size variable. Bug=None TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog. Change-Id: I4c35ba2bcf757231aa2872802eb82d4d50742cd9 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75526 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01device/pci: Limit default domain memory windowNico Huber
When the default pci_domain_read_resources() is used, keep 32-bit memory resources below the limit given by CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a workaround for missing/wrong reservations of chipset resources. This will help to get more stable results from our own allocator, but is far from a complete solution. Indvi- dual platform ASL code also needs to be considered, so the OS won't assign conflicting resources. Most platforms have reserved space between 0xfe000000 and the 4G barrier. So use that as a global default. In case of `soc/intel/common/`, use 0xe0000000 because this is what is advertised in ACPI and there are traces of resources below 0xfe000000 that are unknown to core- boot's C code (PCH_PRESERVED_BASE?). Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top- down allocation. Fixes EHCI w/ top-down in QEMU. Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28soc/intel/xeon_sp: Enable build for IO MarginingNaresh Solanki
This commit enables the build for IO Margining, ensuring that ASPM is disabled and certain FSP knobs are adjusted in coreboot as below 1. Enable DFXEnable 2. Disable PcieGlobalAspm 3. Disable KtiLinkL1En & KtiLinkL0pEn Since the FSP UPD does not provide all the necessary knobs for IO Margining, the following settings need to be applied during the FSP build process: 1. Enable PcdBiosDfxKnobEnabled 2. Disable PchDmiAspm 3. Enable SataTestMode 4. Enable WmphyMargining 5. Disable IioErrorEn TEST=Build for IBM sbp1 board. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26soc/intel/common: Support power limits update for variantsSumeet R Pawnikar
Add support to update power limit values for variants. Until now, each SoC implements this themselves. To avoid code duplication, add this to common code. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26soc/intel/meteorlake: Hook up SaGvFreq, SaGvGear updsBora Guvendik
Hook the SaGvFreq, SaGvGear upds so that mainboard can change the settings via devicetree. Meteor Lake supports 4 SaGv work points and it can dynamically scale the work point based on memory bandwidth utilization. Dynamic gearing technology allows the Memory Controller to run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio of DRAM speed to Memory Controller Clock. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I37169880af4019675374594e90735b5d7d0873b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25soc/intel/mtl/acpi/xhci: Add clock gating supportJeremy Compostella
Implement PS0 and PS3 methods to support xHCI clock gating in S0ix suspend and resume. BUG=b:283989367 TEST=S0iX test passed Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25soc/intel/meteorlake: Enable Key LockerPratikkumar Prajapati
BUG=b:276988831 Platform=Rex Test= inteltool -k ============= Dumping INTEL Key Locker status ============= Key Locker supported : YES AESKL instructions enabled : YES =========================================================== Also, No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen. Boot time delta (using cbmem -t): Without this CL: 963:returning from FspMultiPhaseSiInit 1,299,043 (98,480) With this CL: 963:returning from FspMultiPhaseSiInit 1,324,659 (121,995) Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25soc/intel/meteorlake: Set SaGv work points as enum macroSubrata Banik
This patch adds an enum macro to define the different SaGv work points. The enum macro is named `sagv_wp_bitmap` and it has three values: The goal is to choose the optimal SaGv work point for the target platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group is for workloads that can tolerate lower performance, in order to save power. SAGV_POINTS_0_1: The highest power consumption, but also the highest performance. SAGV_POINTS_0_1_2: A lower power consumption than work point SAGV_POINTS_0_1, but also a lower performance. SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest performance. Set SaGv work points after reviewing the power and performance impact with SaGv set to 1 (Enabled) and various considering various work points between 0-3 being enabled. BUG=b:267879107 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4af0038f2799a458d1b006270068341f65d36609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24soc/intel/meteorlake: Add CPU PortID for GPIO CommunityMarx Wang
Add CPU PortID for GPIO communities in order to calculate IOM Aux Bias data correctly. BUG=b:283044004 TEST=able to detect external display Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-24soc/intel/elkhartlake: Make PCIe root port max payload size configurableMario Scheithauer
The data payload size of PCIe root ports can be set to either 128 (default) or 256 bytes. A bigger payload size can improve PCIe data throughput on the given port. FSP-S provides a parameter to configure this value. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-23soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flagJohnny Lin
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag in case a certain platform may not support this via CMOS data, and the function could in turn calls mainboard defined method in the future. Move the code into soc_util.c. 2. Remove redundant static get_system_memory_map() from cpx/romstage.c and call the soc_util.c one. Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23soc/intel/common: Add RPP-S PCI IDsJeremy Soller
Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22soc/intel/common: Add an error for missing ramtop CMOS entrySean Rhodes
Show an error if an option table is used, and the ramtop entry is not defined on a platform that uses it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-21soc/intel/meteorlake: Add `.final` to check FSP reset pending requestSubrata Banik
This patch adds an API to check FSP reset pending requests. This information is useful to understand if FSP would like boot firmware to issue any reset to complete the silicon initialization. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. BUG=b:282266168 TEST=Able to build and boot google/rex and able to detect FSP reset pending request. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-20soc/intel/quark: Drop supportFelix Singer
As announced in the 4.20 release notes, support for the Intel Quark SoC is moved to the 4.20 branch and dropped from master. Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-19soc/intel/common: Correct the check for ramtop lengthSean Rhodes
The `ramtop_table` is 10 bytes long, so adjust the check to account for this. Also, adjust the wording to make it clear what is required to fix it, should the error be shown. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19soc/intel/jasperlake: Add PsysPmax configChia-Ling Hou
Enable PSYS capability. PSYS is required to safeguard the system stability if no charger IC. BUG=b:281479111 TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196 Reviewed-by: Reka Norman <rekanorman@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19soc/intel/meteorlake: Add igd deviceWon Chung
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in SSDT. BUG=b:277629750 TEST=emerge-rex coreboot then check SSDT on DUT Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19soc/intel: Extend fsp_get_pch_reset_status() to all FSP APIsSubrata Banik
This patch drops the assert check around `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure `fsp_get_pch_reset_status()` can be used by all other FSP APIs to know the status of the pending reset. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. Going forward coreboot needs to implement the corresponding logic to be able to identify any pending platform reset request and execute to complete the silicon initialization flow. BUG=b:282266168 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17console: Add format-checking __printf() to die()Nico Huber
Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)Nico Huber
Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17soc/intel/common: Don't hardcode ramtop offsetSean Rhodes
The `ramtop` can be obtained from the `option.h`, so remove the hardcoded value. Keep the check for the value being byte aligned. Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17soc/intel/alderlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17soc/intel/meteorlake: Handle FSP logo paramsSubrata Banik
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid logo.bmp file if `BMP_LOGO` config is enabled. TEST=Able to see splash screen while booting Intel Meteor Lake RVP with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-16soc/intel/xeon_sp: Drop dummy FADT entryKyösti Mälkki
Specifying types without addresses for PM1B events is not useful. Change-Id: I839208eaecf689a32484b9154647fc66633e5eef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-13acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held
In ACPI 1.0 the processor objects were inside the \_PR scope, but since ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS compatibility, but apart from that the \_PR scope is deprecated. coreboot already uses the \_SB scope for the processor devices everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the format string inside the 3 snprintf statements that use the ACPI_CPU_STRING. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-12soc/intel/apl: Remove set but unused variableArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12soc/intel/common: Define enum types for MKHI group IDs and ME SKUsSridhar Siricilla
The patch defines enum type for MKHI group IDs and ME SKU types instead of macros. TEST=Build code for Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I102e802938a6a664a43a362d90a26755cff8f316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-12soc/intel/common: Remove superfluous cmos_offset from ramtopSean Rhodes
Having `_cmos_offset` in a CMOS offset is superfluous; remove it so the CMOS entry is just `ramtop`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-11soc/intel/apollolake: Only use 8 bits for afterg3Sean Rhodes
In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e) (source Intel document #569262). Only use 8 bits, in the same way as most other Intel SOCs do, for pmc_soc_set_afterg3_en. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()Dinesh Gehlot
The return value of cse_get_bp_info() is an enum integer, where zero means success and non-zero means failure. The function store_cse_rw_fw_version() calls the function cse_get_bp_info() and validates the return value as a boolean causing prematurely returns of the parent API even if cse_get_bp_info() is successful. This patch corrects this logical error by returning only if cse_get_bp_info() fails. TEST=Build and boot google/nivviks and verify that the ISH version info command is only being sent during cold boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-11soc/intel/common: Fix long delay when ME is disabledSean Rhodes
If the ME is disabled with the `me_state` CMOS setting, boot times are approximately 5 seconds longer: 942:before sending EOP to ME 1,240,773 (5,599) 943:after sending EOP to ME 6,263,951 (5,023,177) Total Time: 6,167,443 This is because the current code only checks if the ME is disabled for CSE LITE SKUs. With this patch, boot times are approximately 5 seconds quicker: Total Time: 1,143,932 Tested on `starbook/adl` and `starbook/tgl`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11soc/intel/meteorlake: Increase pcie snoop/non-snoop latencyRavi Sarawadi
This fixes an issue where pcie was not power gating and blocked S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance values to 15.73ms as stated in doc #729123 - MTL External Design Specification. BUG=none TEST=Boot google/rex, print/check values. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-10soc/intel: Clean up some includesKyösti Mälkki
Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latencyBora Guvendik
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and snoop latency tolerance. Add config to let SoC overwrite the common code settings if needed. BUG=none TEST=Boot google/rex and print/check if able to overwrite values. Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-10soc/intel/elkhartlake: Make hard drive type for SATA ports configurableMario Scheithauer
Intel's EHL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-09mb/google,intel: Use common ChromeEC code for lid shutdownKyösti Mälkki
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09sb,soc/amd,intel: Apply minor FADT fixesKyösti Mälkki
Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09soc/intel/xeon_sp/spr: Drop spurious FADT fieldsKyösti Mälkki
Assigning duty_offset while duty_width==0 has no purpose. Under intel/common/block, previous assignment for fadt->gpe0_blk resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns value matching pmbase + 0x60. Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08soc/intel/early_graphics: support to allow early graphics GPIO configTarun Tuli
For early Sign of Life to work, we may need certain pin configurations very early in boot (e.g. HDMI). This may happen before romstage GPIOs are configured, and bootblock is not suitable for field upgrading existing devices. Add a separate GPIO table that can be configured when early graphics is invoked. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on HDMI enabled variants Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08soc/intel/meteorlake: Apply large cbmem buffer size for FSP debugSubrata Banik
This patch ensures that the PRERAM_CBMEM_CONSOLE_SIZE and CONSOLE_CBMEM_BUFFER_SIZE hold a larger cbmem buffer size to contain the entire FSP debug serial log. The existing implementation was not appropriate, where the larger cbmem size was even applicable for serial AP firmware (w/o FSP debug) image as well. This change is necessary to ensure that the FSP debug serial log is always available, even in cases where the cbmem buffer size is limited. BUG=b:280481298 TEST=Able to build and boot google/rex with non-FSP serial AP image and with FSP serial AP image. Able to see the AP log completely inside the cbmem. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib35780fd558c8b6d9aa2e17241131ea4a58c2b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/75030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-06soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwiseSubrata Banik
This patch makes CSE sync in romstage default enabled unless ramstage config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it. TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-05src/soc/intel: Document meaning of variablesMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05soc/intel/spr: Fix copy paste issue in error messagesFelix Singer
The commit a0b199c6b483 ("soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error messages. The error messages should mention the Intel platform SPR instead of CPX. Fix that. Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-02soc/intel/alderlake: Disable C1E on RPL CPUsJoey Peng
Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-05-02soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN configSubrata Banik
At present the problem has only been reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this patch ensures to select applicable W/A config to read FSP return status from the FSP Reset HOB. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Without this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns into coreboot, the `status` from the FSP API is reset to `0` instead 0x40000003. Hence, coreboot avoid hitting the reset. With this patch: IshInit() Start IshDisable() Start IshPerformGlobalReset() .... .... FSP returning control to Bootloader with reset required return status 40000003 FSP: handling reset type 40000003 <-- coreboot is able to understand the reset request in proper. GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02soc/intel/common: Introduce API to get the FSP Reset StatusSubrata Banik
This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option to handle broken FSP API return status issue. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-01soc/intel/adl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/banshee, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/intel/tgl: Unhide PMC, IOM ACPI devices from OSMatt DeVillier
These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/drobit, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW SyncAnil Kumar
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-04-29sb,soc/amd,intel: Drop include <cpu/x86/smm.h>Kyösti Mälkki
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28soc/intel/common/block/pmc: Sort Kconfig in alphabetical orderChristian Walter
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28vga: Change the arguments of vga_write_text to support extended ASCIIHsuan Ting Chen
VGA defined the extended ASCII set based on CP437, but the function vga_write_text() accepts a signed char array. This will cause unnecessary confusion that if we want to print u with umlaut (code=129 in CP437), we need to explicitly cast it to -127 in signed char. Since we still want to leverage the built-in string utilities which only accepts const char*, we still need to cast it to signed char while processing, and cast it back to unsigned once we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-27ACPI: Make FADT entries for SMI architecturalKyösti Mälkki
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-26intel/mtl: Add get_cse_ver_from_cbfs functionAshish Kumar Mishra
This patch implements helper function get_cse_ver_from_cbfs() to retrieve the CSE Lite version from CBFE RW's metadata and calls the helper function from cse_check_update_status() TEST=Verified CSE Lite version in coreboot boot log Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-04-26soc/intel: Don't report _S1 state when unsupportedArthur Heymans
Since skylake Intel hardware does not support this sleep state. Trying to enter S1 by having the OS enter sleep results in a system hang on at least Alder lake (prodrive/atlas). CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices support 'skylake style' PMC PCI device for ACPI registers. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26soc/intel/common: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
For the first IOAPIC, use the common MADT generator with default IRQ overrides. Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPICKyösti Mälkki
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADTKyösti Mälkki
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms' implementations of adding IOAPIC and IRQ override entries for ACPI MADT tables. Platforms that have a more complex MADT may continue to add custom entries using CUSTOM_ACPI_MADT. Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26arch/x86/ioapic: Promote ioapic_get_sci_pin()Kyösti Mälkki
Platform needs to implement this to provide information about SCI IRQ pin and polarity, to be used for filling in ACPI FADT and MADT entries. Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26soc/intel: Introduce ioapic_get_sci_pin()Kyösti Mälkki
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors. This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work. Care should be taken that ioapic_get_sci_pin() is called after platform code has potentially changed the routing from the default. It appears touched all platforms except siemens/mc_aplX currently program SCI as IRQ9. Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-22soc/intel/meteoerlake: set power limits dynamicallySumeet R Pawnikar
Set power limit values dynamically based on Meteor Lake CPU TDP and PCI ID of SKU. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values for 15W SKU on Rex board Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function staticSubrata Banik
The patch makes `cse_get_fpt_partition_info()` AP local/static as all the references to this function are in local to the cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 08:57:55 +0000